How AI chips
are made

Design is the only stage of the supply chain without a factory, and the US government has already restricted it by letter. In late May 2025 the government required a license to sell chip design software to anyone in China ¹. Cadence cut off its Chinese customers until the government lifted the rule on 2 July ¹.

How it works

How a chip is designed

1. 01A blueprint
2. 02One tick
3. 03Too far
4. 04Placed closer
5. 05Checked

Paused

Making a chip starts with design, which turns an idea into a complete blueprint. The blueprint fixes where each of the chip’s billions of switches sits and how each one is wired to the others.

1. A blueprint. Making a chip starts with design, which turns an idea into a complete blueprint. The blueprint fixes where each of the chip’s billions of switches sits and how each one is wired to the others.
2. One tick. The chip works in ticks, each less than a billionth of a second. On every tick a signal leaves a register, a small store that holds one number, and it has to cross its wire to the next register before the next tick.
3. Too far. If the next register sits far away, the wire is long. The signal is still on its way when the next tick comes, so it arrives too late.
4. Placed closer. Design software from three companies, Synopsys, Cadence and Siemens, places the parts and wires them together. Here it moves the register closer, and the signal arrives in time.
5. Checked. The software checks that every signal on the chip arrives in time, and a chip factory accepts only designs that pass. The factory then prints the blueprint onto silicon through stencils, and changing it after that costs new stencils and several months.

Simplified. Not to scale. The floorplan follows a GPU die. One tick, less than a billionth of a second, is slowed to about two seconds.

Design runs in five stages, all in software, and each stage's output is the next one's input.

• Architecture. Engineers fix the shape of the chip: the width of the block that multiplies numbers, the amount of fast on-chip memory beside it and the number of high-bandwidth memory stacks along the chip's edges. The output is a plan.
• RTL. Engineers write the plan as register-transfer-level code, RTL, in the hardware language SystemVerilog. A register is a small store on the chip that holds one number. On each tick of the chip's clock, every register takes its next value at the same moment. The code says what every register holds on every tick. The output is a text description of the whole chip.
• Verification. A large team checks that the code does what the plan says. They run it in simulation and prove parts of it correct with mathematics. They also load it into emulators, cabinets of reprogrammable chips that behave like the design, so the chip's own software can boot before any silicon exists.
• Physical design. Software swaps each piece of the code for a logic cell, a small ready-made circuit the foundry has already proved it can make. It then places the cells on the chip, wires them together and proves that every signal arrives in time.
• Tape-out. Software turns the placed layout into pattern files for the mask shop. First it pre-distorts each shape so that the shape prints as drawn, a step called optical proximity correction. Then it cuts the layout into the files a mask writer reads, a step called mask data preparation. Handing those files to the mask shop is called tape-out.

All that checking exists because each revision after tape-out, called a respin, needs at least some new masks ². In 2022 SemiAnalysis put a full mask set at more than $1 million at 28 nm and more than $10 million at 7 nm ². The nanometer labels name process generations, called nodes, each finer than the last, and no longer measure anything. That year SemiAnalysis also expected 3 nm sets to push into the $40 million range ². Its May 2026 primer still puts a leading-edge mask set at $40 million, and a single leading-edge respin at $50 million to $100 million ³.

The same 2022 SemiAnalysis article reported that startups had taken chips on TSMC 7 nm, then a leading-edge process, from design to tape-out for $50 million to $75 million, everything included ². Using a different measure, CSIS put the cost of developing a leading-edge 2 nm chip at about $725 million in September 2026 ⁴. It put the cost of developing a 28 nm design in the late 2000s at $48 million ⁴.

Variants and trade-offs

Merchant GPU versus custom ASIC

Nvidia designs its Blackwell GPU once and sells it to everyone, so the buyer gets mature software and a resale market. A custom accelerator, an ASIC, is built for one company's own workload. It handles a narrower range of tasks and is tuned to that workload. Google's seventh-generation tensor processing unit, Ironwood, carries 192 GB of memory per chip, six times its predecessor's, and delivers twice the performance per watt ⁵.

The EDA flow

Chip design software is known as electronic design automation, or EDA. Three complete EDA flows exist, each a set of tools that covers every step from code to signoff ³. Changing the synthesis tool, which swaps the code for logic cells, means re-running the steps that follow: placing and wiring the cells, signoff and physical verification ³. Foundries also specify which signoff tools their customers must use for tape-out ³.

Inside some steps of the flow, one vendor holds most of the market. Synopsys alone has more than 90 percent of the market for static timing analysis, the check that proves a chip will run at its rated speed ³.

Buy the IP or build it

Design houses license ready-made circuit blocks, known as intellectual property or IP, including the processor cores, the interface controllers and the blocks that drive high-bandwidth memory. Arm licenses processor designs. In fiscal 2026 it reported $4.92 billion of revenue, $2.61 billion of it royalties ⁶. It said it held about 50 percent of processor compute at the top cloud firms ⁶.

In 2026 Arm also launched the Arm AGI CPU, its first production silicon product ⁶. By May 2026, servers built on it could be ordered from ASRock, Lenovo, Quanta and Supermicro ⁶.

The memory interface is hard to design, because its signals have to stay on time across thousands of microscopic solder bumps into a stacked memory die.

RISC-V is an open instruction set, the basic list of commands a processor understands, and it needs no license. Small RISC-V processors handle control tasks on the chip, and Nvidia uses them in every GPU ⁷.

Chiplets

The reticle limit caps the size of a single die, one piece of silicon ⁸. That limit is the largest area a scanner, the machine that prints the chip's pattern, can expose in one shot. Many large accelerators are built from chiplets, several smaller dies wired together, and UCIe is an open industry standard for the links between them inside a package ⁹. Version 3.0 of UCIe adds 48 and 64 GT/s data rates ⁹. Broadcom's 3.5D XDSiP platform packs more than 6,000 mm2 of silicon and 12 high-bandwidth memory stacks into one package ⁸.

Who makes it

Design software and licensed blocks were an $18 billion market in 2025 ³. Synopsys, Cadence and Siemens EDA took more than 85 percent of it, counting Ansys as part of Synopsys ³. No other vendor had more than 5 percent of any core category ³.

Synopsys is the largest. Its own results put revenue at $7.054 billion for the fiscal year to 31 October 2025, with Ansys, bought that July, contributing $756.6 million ¹⁰. Cadence, whose year ends in December, took $5.297 billion in calendar 2025 ¹¹.

The two fiscal years do not line up, so any total for this market depends on which twelve months are counted. It also depends on how much of Ansys it includes, because Ansys sells to other industries too. SemiAnalysis counts Synopsys at $8 billion for calendar 2025 with Ansys included ³. It puts 31 percent of Ansys's business in semiconductors and high technology, 22 percent in aerospace and 18 percent in automotive ³.

Some chip firms also build custom accelerators to a customer's design and sell the finished chips. Broadcom booked $16.7 billion of AI semiconductor revenue in the third quarter of fiscal 2026, up 221 percent year over year ¹². That figure covers both its custom AI accelerators and its AI networking chips ¹².

In October 2025 OpenAI and Broadcom said they would deploy 10 gigawatts of OpenAI-designed accelerators ¹³. Broadcom would turn the design into silicon and supply the Ethernet networking around it ¹³. In April 2026 Broadcom extended its Meta partnership to multiple gigawatts of MTIA, Meta's in-house chip, and the first 2 nm AI accelerator ¹⁴.

Marvell, another US firm, also builds custom accelerators. Below Broadcom and Marvell are the Taiwanese design-service houses. They carry a customer's circuit list all the way to a finished mask set on TSMC's newest nodes. One of them, Alchip, reported $992 million of revenue in 2025 ¹⁵.

Chip design engineers are spread across more countries than these firms are. India alone has nearly 20 percent of the world's chip designers ¹⁶.

The chokepoint

Before the 2025 letters, a narrower control already applied. Since 14 October 2022, design software specially made for chips with gate-all-around transistors has needed a US export license for national-security reasons ¹⁷. The rule calls that transistor design key to processes at 3 nm and below ¹⁷. That license requirement covers exports to China ¹⁸. The control carried out a December 2021 decision of the Wassenaar Arrangement, a group of countries that coordinate export controls ¹⁷.

In late May 2025 the US Bureau of Industry and Security, the agency that issues export licenses, told the design-software vendors that sales to China now needed a license ¹. Cadence got its letter on 23 May ¹. The letter required a license to export design software classified 3D991 and 3E991 to any party in China, or to a Chinese military end user anywhere ¹. Synopsys got its letter on 29 May and a second letter lifting the requirement on 2 July ¹⁹.

Unlike the 2022 control, the 2025 requirement came from the United States alone and took effect immediately. Synopsys's China revenue fell from 16 percent of its total in fiscal 2024 to 12 percent in fiscal 2025 ³. SemiAnalysis links the decline to tighter export restrictions and to local design-software companies winning share at mature nodes ³. SemiAnalysis also quoted Synopsys's management saying that companies Synopsys cannot sell to look for alternatives, typically local design-software and licensed-block companies ³.

In October 2025 CSIS found that only a few companies, Cadence, Synopsys and Siemens, make design software that supports the entire chip design flow of more than 40 steps ²⁰. In a January 2021 report built on 2019 market data, CSET at Georgetown University found that one Chinese firm, Empyrean, could reportedly run a complete design flow only for certain analog and mixed-signal chips ²¹. Mixed-signal chips combine analog and digital circuits. For all other chips, Chinese designers then relied on US tools ²¹. The report found that other Chinese tools covered only narrow parts of the design flow or supplemented US tools, and largely did not support processes at 14 nm and below ²¹.

In its 2025 annual report, filed in April 2026, Empyrean says it now has complete design flows for analog, memory, radio-frequency and flat-panel display circuits ²². It says its digital tools cover 80 percent of the main tools for digital design ²². The same report lists foundry certifications for its circuit simulator at 8, 5 and 4 nm and for its physical verification tool, the final layout check, at 28 nm ²². But CSIS found that as of 2025 Chinese design tools were still far from replacing the full range of advanced capabilities US firms offer, especially for 5 nm and 3 nm chip design ²⁰.

China can design accelerators, but it cannot finish one at the leading edge without foreign tools, or build what it designs without foreign equipment. SMIC, a Chinese foundry, makes Huawei's chips. In June 2024 CSET found that SMIC's limited 7 nm capacity forced Huawei to choose between making its most advanced phone chips and its AI chips ²³.

On Epoch AI's estimates, Huawei's flagship chip for 2026, the Ascend 950, delivers about half the computing performance of Nvidia's H100, which began shipping in 2022 ²⁴. Epoch puts Nvidia's B300 at 6.75 times the 950's theoretical peak performance ²⁴. Epoch's median estimate is that Huawei will make about 1.5 million Ascend chips in 2026, against 5.9 million for Nvidia ²⁴. On those estimates, Huawei's 2026 output would carry less than 4 percent of the computing power Nvidia ships that year ²⁴.

Epoch puts Huawei's chips three to four years behind Nvidia's until at least 2030, for three reasons ²⁴. SMIC cannot pack transistors as densely as TSMC, which makes Nvidia's. Chinese memory makers are only starting to produce high-bandwidth memory. And Huawei's software for programming its chips is far less mature than Nvidia's ²⁴.

The world market for silicon wafers was $11.4 billion in 2025, on 12,973 million square inches shipped ¹. That is a small fraction of Nvidia's data center revenue, which reached $193.7 billion in the fiscal year to January 25, 2026 ².

How it works

From sand to wafer

1. 01Refine
2. 02Grow
3. 03Slice
4. 04Polish

Paused

Silicon starts as sand and rock. It is refined into rods so pure that, of every hundred billion atoms, fewer than one is anything else.

1. Refine. Silicon starts as sand and rock. It is refined into rods so pure that, of every hundred billion atoms, fewer than one is anything else.
2. Grow. The rods are melted. A seed crystal touches the melt and is drawn slowly up, turning, and the silicon freezes onto it as one long crystal.
3. Slice. A wire saw slices the crystal, called an ingot, into thin discs.
4. Polish. Each disc is ground, etched and polished until it is flat to within a few atoms, right out to the edge.

Simplified. The ingot and the machines are not drawn to scale.

Silicon starts as quartzite, a rock that is silicon bound to oxygen. An arc furnace melts it with carbon, and the carbon takes the oxygen away as gas, leaving rough silicon metal. Refiners turn the metal into a gas, trichlorosilane, and distill it, because the impurities boil at other temperatures and stay behind.

In the next step, the Siemens process, the clean gas flows over silicon filaments heated inside a bell jar. On the hot surface the gas breaks apart and its silicon settles onto the filaments. Over days the filaments thicken into gray rods of polysilicon. Everything downstream is made from those rods. Polysilicon comes in two ultra-high-purity grades, one for semiconductors and one for solar cells, and chips use the semiconductor grade ⁵.

A grower melts the polysilicon at about 1,420 degrees Celsius, hotter than lava, and pulls a single crystal out of it by the Czochralski method ³. The grower lowers a small seed crystal on the end of a rod to the surface of the melt and draws it back up, slowly turning. Silicon freezes onto the seed in the seed's own atomic pattern, and a cylinder, the ingot, grows beneath it. The pull starts with a thin neck so that flaws from the seed's first contact with the melt stay in the neck and never reach the ingot. Boron or phosphorus stirred into the melt, a step called doping, sets how readily the wafer conducts and whether negative or positive charges carry its current.

A wire saw, a web of fine wire running through abrasive, slices the ingot into discs. The maker then laps each disc, grinding both faces flat between rotating plates. It etches off the damaged surface with chemicals, then polishes the disc to a mirror with colloidal silica, a slurry of silica particles far too small to see. Almost every step throws material away.

Epitaxial wafers get one more layer of near-perfect silicon, grown on top at about 1,200 degrees Celsius ³. That is still hot enough to glow orange.

Variants and trade-offs

Polished versus epitaxial

A polished wafer is a doped single crystal polished to a mirror finish ³. An epitaxial wafer is a polished wafer with a thin layer of single-crystal silicon grown on top ³. The transistors are built in that layer, so its quality sets the lowest leakage the chip can reach. It also sets the chip's risk of latch-up, an unintended short circuit between power and ground. SEMI, the industry association, credits the 2025 rise in shipments to AI-driven demand for advanced epitaxial wafers for logic chips and polished wafers for high-bandwidth memory ¹.

Silicon on insulator

In a silicon-on-insulator (SOI) wafer, a buried layer of oxide, which is glass, separates a thin working layer of silicon from the bulk beneath. Nearly all SOI wafers are made with Soitec's Smart Cut process ⁶. Soitec's SOI product lines include RF-SOI for radio chips and fully depleted SOI (FD-SOI), and its markets run from mobile communications to cloud AI ⁶. But SEMI tied the AI-driven growth in logic chips to advanced epitaxial wafers ¹.

Who makes it

The Center for Security and Emerging Technology (CSET) at Georgetown University named five key wafer firms in a January 2021 brief ⁷. They were Shin-Etsu and SUMCO of Japan, GlobalWafers of Taiwan, Siltronic of Germany and SK Siltron of South Korea ⁷. CSET also listed nine Chinese-owned producers, among them Zhonghuan, Simgui, ZingSEMI and Finland's Okmetic, but said they generated little revenue in comparison ⁷.

As of 2018, five Chinese firms were making or planning 300 mm wafers ⁷. In its October 2025 listing prospectus, Eswin, a Chinese wafer maker, counts seven Chinese firms, itself included, making 300 mm wafers at scale ⁸. Their combined capacity was 2.94 million wafers a month at the end of 2024 ⁸.

The chart shows shares of 2023 sales from a survey by Fuji Keizai, a Japanese research firm ⁹. Japan's Ministry of Economy, Trade and Industry reproduced the figures in a December 2025 strategy deck ⁹. The deck prints only Japan's 53 percent, so the other shares are read off its chart ⁹. The chart gives no separate share to Chinese or US companies ⁹. Siltronic's April 2026 investor presentation says the top five wafer makers serve around 75 percent of the market, based on revenue in the first three quarters of 2025 ⁴.

The wafer makers' 2025 results show strong AI demand and a slump in demand for chips made on older, mature nodes.

• Shin-Etsu. Its parent's electronics materials segment sold ¥1,015.7 billion in the year to March 2026, up 9 percent ¹⁰. AI-related demand stayed strong and demand in other sectors began to rise, lifting sales of silicon wafers, photoresist and photomask blanks ¹⁰. The segment also sells rare earth magnets and other materials, and the results release does not break out wafer sales ¹⁰. So the figure cannot be compared with the wafer revenue of the other firms listed.
• SUMCO. Sold ¥409.7 billion and still lost ¥11.8 billion, as operating profit fell from ¥36.9 billion to ¥1.3 billion ¹¹. In the same year it added leading-edge 300 mm capacity and reorganized production of 200 mm and smaller wafers, where demand stayed weak ¹¹.
• Siltronic. Lost €77.9 million on €1,346.7 million of sales while investing €369.1 million, with its new Singapore fab as the focus ¹².
• GlobalWafers. NT$60.6 billion of revenue, down 3.24 percent in local currency ¹³.

Worldwide, the wafer area shipped rose 5.8 percent in 2025, but revenue fell 1.2 percent ¹. SEMI attributes the softer revenue mostly to traditional chip applications, where demand and pricing had yet to improve ¹.

China made 1.50 million metric tons of polysilicon, the raw material, in 2023, about 93 percent of world output ¹⁴. Solar-grade material was an estimated 98 percent of that output and electronic-grade 2 percent ¹⁴. The Commerce Department found in 2026 that semiconductor-grade polysilicon makes up only 2.4 percent of global production, a split close to China's ¹⁵. These figures alone do not show whether Chinese polysilicon goes into chips.

Siltronic put the 2025 market for electronic-grade silicon at $1.4 billion, with five major suppliers, none of them Chinese: Wacker, Hemlock, OCI, Tokuyama and Mitsubishi ⁴.

Siltronic of Germany describes itself as the only Western-based maker among the top five wafer makers, based on revenue in the first three quarters of 2025 ⁴. GlobalWafers opened a $3.5 billion plant in Sherman, Texas in May 2025, the first production line of its kind built in the United States in over twenty years ¹⁶. The same day it announced another $4 billion for phases three and four in Sherman ¹⁶. The US government had awarded it up to $406 million under the CHIPS incentives program for wafer plants in Texas and Missouri ¹⁷.

Presidential Proclamation 11052, signed August 6, 2026, sets a minimum import price of $100 per kilogram for polysilicon ingots and wafers from December 4, 2026 ¹⁵. From the same date it adds an extra 15 percent duty on imported ingots and other listed products made from polysilicon ¹⁵. A September 2026 Commerce rule meant to stop stockpiling before the duties start lists tariff code 3818.00.0040 among the products it covers ¹⁸. That code covers round, doped, single-crystal silicon wafers ¹⁹.

Commerce may approve plans to build US polysilicon, ingot, wafer or solar cell plants whose construction starts by January 20, 2029 ¹⁵. Firms with approved plans can import equipment and some of those products without the new duties ¹⁵.

The chokepoint

China makes most of the world's polysilicon, but in 2019 its firms had almost no share of the wafer market. As of 2019 Chinese firms held under 5 percent of the wafer market and under 1 percent of the 300 mm market ⁷. As of 2018, Chinese producers made 12 percent of the wafers for Chinese-headquartered 300 mm fabs, against 18 percent for 100 to 200 mm fabs ⁷.

Eswin, mainland China's largest maker of 300 mm wafers, says it ranked sixth in the world with about 7.7 percent of global 300 mm shipments in the first half of 2026 ²⁰. Its October 2025 Shanghai listing prospectus, drawing on SEMI data, estimates that the five largest makers shipped about 79 percent of 300 mm wafers in 2024 ⁸. It puts Eswin at about 6 percent and all other makers at about 15 percent ⁸.

Making the smoothest, high-purity 300 mm wafers takes considerable know-how that is hard to write down ⁷. Customers have to qualify a new wafer plant before they buy from it, and Siltronic completed key customer qualifications at its new Singapore fab in July 2025 ⁴.

In SEMI figures from November 2020 cited by CSET, 99.7 percent of world fab capacity at 45 nm and below used 300 mm wafers ⁷. SEMI estimated that 300 mm wafers made up about 78.8 percent of all wafer area shipped worldwide in 2025, according to Eswin's 2025 annual report summary ²¹.

The last increase in wafer size, to 300 mm, happened in 2002 ⁷. Bigger discs make printing, or photolithography, a bigger share of the processing cost ⁷. A 2013 University of Texas lecture cited by CSET put photolithography at half the cost of processing a 300 mm wafer, against a quarter for a 150 mm one ⁷. Wafers are still produced in diameters of up to 300 mm ¹.

Some GPU dies fill the whole area a lithography tool can print in one exposure. One fatal defect on such a die ruins far more silicon than one on a small chip. Extreme-ultraviolet printing also stays in focus over only a tiny range of heights (see Lithography), so the disc has to be flat at every point. SEMI's wafer group says the move to sub-3nm processes is raising requirements for wafer quality and consistency ¹.

A chip fab uses a few hundred chemicals and gases, and a shortage of any one of them can stop it. The French gas company Air Liquide alone supplies more than 200 molecules and roughly 50,000 cylinders a year ¹.

How it works

The resist has to change only where the light lands. It also has to react fast enough for the scanner, the machine that projects the pattern, to expose each patch of the wafer in milliseconds.

Since the 1990s the standard has been chemically amplified resist. In resists for 248 nm and 193 nm light, a photon absorbed in the film can free an acid molecule, and nothing more happens until the wafer is baked. In the bake, each acid molecule sets off hundreds of reactions around itself that turn the film soluble, so a little light does a lot of chemistry. The wash then takes away the exposed film and leaves the rest. The 248 nm light comes from a krypton fluoride (KrF) laser. The 193 nm light comes from an argon fluoride (ArF) laser and shines through a layer of water, which sharpens the image.

That chemistry works less well with extreme ultraviolet (EUV) light (see Lithography). An absorbed EUV photon instead knocks electrons loose, and a cascade of lower-energy secondary electrons makes the chemical changes in the resist ³. A 13.5 nm EUV photon carries about fourteen times the energy of a 193 nm one, so the same dose of light arrives as far fewer photons. With fewer photons, random variation in where each one lands matters more. It shows up as ragged line edges and missing contact holes, the small wells that join one layer of wiring to the next.

Resist makers responded with metal-oxide resists, which are built on clusters with a tin-oxide core and absorb more of the EUV light than chemically amplified resists ⁴. In 2021 the Japanese resist maker JSR agreed to buy Inpria, an Oregon maker of these resists ⁵.

The other chemicals and gases put material on the wafer, take it off or keep it clean. Bulk gases arrive by the metric ton, specialty gases in grams. Silane gas carries the silicon for new layers into the chamber that holds the wafer. A plasma tears nitrogen trifluoride into charged fragments, which scrub the chamber walls clean between wafers. Hydrofluoric acid cleans the wafer itself. Polishing slurries grind each new layer flat before the next goes on.

Sputtering targets are slabs of pure metal. A plasma knocks atoms off them, and the atoms settle on the wafer as thin metal films, including the barrier and seed layers for copper wiring ⁶. Electroplating then fills in the copper wiring itself ⁷. Filters and wafer carriers keep contamination out.

Variants and trade-offs

Each resist class is made for one kind of lithography, such as EUV, ArF immersion, ArF, KrF or i-line ⁸.

Who makes it

In a January 2021 brief, Georgetown University's Center for Security and Emerging Technology (CSET) put Japan's share of the semiconductor photoresist market at 90 percent, citing a 2019 estimate ⁸. The brief put most of the rest with US and South Korean firms ⁸. In a December 2025 strategy presentation, Japan's Ministry of Economy, Trade and Industry (METI) published figures from a separate survey by Fuji Keizai, a Japanese market research firm ². That survey counts sales by company nationality and puts Japanese companies at 77 percent in 2021 and 78 percent in 2023, with American and South Korean companies next ².

CSET's January 2021 brief lists five Japanese resist makers: JSR, Tokyo Ohka Kogyo, Shin-Etsu Chemical, Fujifilm and Sumitomo Chemical ⁸. It also lists Dongjin of South Korea, the American firms DuPont, EMD Performance Materials and Inpria, and four Chinese firms ⁸. Qnity Electronics, the former DuPont electronics business, says in its 2025 annual report that it offers lithography materials for every wavelength, including EUV ⁹. In its 2025 annual report summary, the Chinese firm Hubei Dinglong said China had yet to reach large-scale production of advanced resist for 248 nm, 193 nm or EUV printing ¹⁰. The firm also said three of its own resists for 248 nm and 193 nm printing had moved into stable volume supply ¹⁰.

A vehicle of Japan Investment Corporation, a state-backed fund, bought 84.36 percent of JSR's shares at ¥4,350 each in a tender offer that closed on 16 April 2024 ¹¹. JSR's shares were delisted from the Tokyo Stock Exchange on 25 June 2024 ¹².

Tokyo Ohka Kogyo sold ¥139,668 million in the first half of fiscal 2026, up 25.1 percent, as strong demand for AI servers in data centers raised demand for chips ¹³. Fujifilm planned to raise its polishing-slurry capacity at Kumamoto by about 30 percent from January 2025 ¹⁴. It also scheduled new production and quality-evaluation equipment for EUV resist at Shizuoka and Pyeongtaek to start in October 2025 ¹⁵.

World sales of wafer fabrication materials reached $45.8 billion in 2025, and sales of packaging materials reached $27.4 billion ¹⁶.

In electronic gases, CSET named Merck, Air Products and Air Liquide as the market leaders in January 2021 ⁸. Air Liquide's electronics business sold €2,465 million in 2025, 9.1 percent of group revenue ¹. SK Specialty has made nitrogen trifluoride since 2001, when it became the first company to produce the gas in South Korea ¹⁷. Kanto Denka Kogyo refines its own fluorine gas and turns it into specialty gases for deposition, etching and cleaning ¹⁸. Stella Chemifa makes ultra-high-purity hydrofluoric acid for chipmaking ¹⁹. Morita Chemical Industries sells an electronic-grade hydrofluoric acid ²⁰.

CSET's January 2021 brief, drawing on 2019 market reports, put five firms at more than 60 percent of the wet chemicals market ⁸. It put DuPont and Cabot Microelectronics at about 56 percent of a $790 million market for polishing slurries ⁸. Counting by company nationality, the same Fuji Keizai survey puts Japanese companies at 51 percent of polishing-slurry sales and 59 percent of high-purity cleaning-liquid sales in 2023 ². Both shares were 49 percent in 2021 ².

Cabot Microelectronics renamed itself CMC Materials in October 2020 ²¹. The American firm Entegris completed its purchase of CMC Materials on 6 July 2022 ²². DuPont separated its electronics business into an independent company, Qnity Electronics, on 1 November 2025 ²³. Qnity sells polishing slurries and pads ²⁴.

In sputtering targets for semiconductors, JX Advanced Metals puts its own share of the world market at about 65 percent as of fiscal 2026 ²⁵.

The chokepoint

Supply at this stage has been disrupted three times since 2019, twice by governments and once by a war.

In July 2019 Japan put photoresist, hydrogen fluoride and fluorinated polyimide under individual export licenses for South Korea, so each export contract needed its own license ²⁶. Japan had supplied more than 90 percent of South Korea's imports of two of the three ²⁶. Its hydrogen fluoride exports to South Korea then fell 87.9 percent ²⁶. Japanese photoresist exports to South Korea did not fall, possibly in part because Japan allowed three-year bulk licenses for some resist sales in December 2019 ²⁶.

South Korea bought more hydrogen fluoride from the United States and Taiwan and more photoresist from Belgium ²⁶. Production of all three chemicals rose inside South Korea ²⁶. The rise came both from South Korean firms and from Japanese companies' affiliates in South Korea ²⁶.

Researchers at Japan's Research Institute of Economy, Trade and Industry (RIETI) found that Japanese hydrogen fluoride exports to the United States rose ²⁶. They say some Japanese supply may have reached South Korea by way of the United States ²⁶. Japan ended the individual licenses on 23 March 2023, when it put exports of the three chemicals to South Korea under its bulk export license system ²⁷.

In 2022 Russia invaded Ukraine, which supplied about 70 percent of the world's neon and 90 percent of the semiconductor-grade neon used by US industry ²⁸. Gas mixtures containing neon power the lasers in lithography scanners ²⁸. Many chipmakers had added to their gas stockpiles after Russia annexed Crimea in 2014 ²⁸. Samsung, SK Hynix, Renesas and Rohm reported adequate neon supplies from China ²⁸.

At this stage, China's export controls cover metals. On 3 July 2023 China announced that exports of gallium and germanium would need licenses from 1 August ²⁹. On 3 December 2024 it said it would in principle grant no licenses to export gallium, germanium, antimony or superhard materials to the United States ³⁰. On 9 November 2025 it suspended that ban until 27 November 2026 ³¹. In February 2026 the US Geological Survey put China's share of world production of primary low-purity gallium at 99 percent ³².

The White House set out a trade deal with China on 1 November 2025 ³³. Under it, China also agreed to issue general licenses for exports of gallium, germanium and antimony for the benefit of US end users and their suppliers ³³.

In the United States, germanium goes mainly into fiber optics, infrared optics, semiconductors and solar cells, and radiation detectors ³⁴. Of the gallium used in the United States, 73 percent went into integrated circuits built on gallium arsenide or gallium nitride ³². Another 26 percent went into optoelectronic devices such as LEDs and laser diodes ³². Gallium is recovered mostly as a byproduct of processing bauxite, the ore that aluminum is made from ³². Germanium comes from certain zinc ores and coal deposits, so supply of both depends on another industry's economics ³⁴.

Germanium metal averaged $4,100 a kilogram in 2025, against $1,392 in 2023 ³⁴. US imports of the metal fell 67 percent in 2025 because of China's ban ³⁴. The US Geological Survey estimated that a total Chinese ban on gallium and germanium exports could cut US GDP by $3.4 billion ³⁵.

A slower risk is the European Union's proposed restriction on PFAS, the long-lived fluorinated chemicals. These chemicals are used throughout a fab. The photoacid generators that free the acid in resist are fluorinated, and so are etch gases, chamber liners, pump seals and filter membranes.

The national authorities of Denmark, Germany, the Netherlands, Norway and Sweden prepared the proposal and updated it after evaluating more than 5,600 comments ³⁶. ECHA, the EU chemicals agency, published the updated proposal on 20 August 2025 ³⁶. The updated proposal assessed options that would let electronics and semiconductor makers keep using PFAS where the risks can be controlled ³⁶.

In March 2026 ECHA's two scientific committees backed an EU-wide restriction with targeted derogations, or exemptions ³⁷. One committee gave its backing in a final opinion and the other in a draft, and their evaluation is due to finish by the end of 2026 ³⁷. The European Commission will decide in consultation with the member states ³⁶.

ASML sold 327 lithography systems in 2025, 48 of them extreme ultraviolet (EUV) ¹. Nobody else makes EUV systems ².

How it works

The stencil is called a photomask, and the machine a scanner (see Photomasks and pellicles).

The wafer is coated with photoresist, a film that changes wherever light touches it. The mask holds one layer of the circuit as a pattern of clear and dark areas, drawn at four times its size on the chip. The machine shines light through the mask, shrinks the image four times with a lens, and lands it on the film.

A wash then removes the film where the light hit, leaving the pattern standing on the wafer. The next machine etches that pattern into the wafer or fills it with metal. Then the film is stripped and the next mask goes in. A chip takes dozens of masks, one per layer.

How lithography prints a chip

1. 01Coat
2. 02Stencil
3. 03Shrink
4. 04Wash
5. 05Repeat

Paused

The wafer is coated with a thin film that changes wherever light touches it.

1. Coat. The wafer is coated with a thin film that changes wherever light touches it.
2. Stencil. A stencil, called a mask, holds the pattern for one layer of the chip, drawn four times larger than life.
3. Shrink. Light shines through the stencil, and a lens shrinks the image four times and lands it on the film.
4. Wash. A wash removes the film wherever the light landed, and the pattern is left on the wafer.
5. Repeat. The machine steps across the wafer, printing one patch at a time, each about the size of a postage stamp.

Simplified. The newest machines, which use extreme ultraviolet light, carry the image with mirrors in place of a lens.

The image from one mask covers a patch about 26 by 33 mm. The wafer moves under the lens one patch at a time, close to a hundred patches per wafer. ASML's own wafers-per-hour rating for an EUV scanner assumes 96 of them ⁴. Before the wafer is exposed, the machine measures alignment marks printed in earlier layers so the new layer lines up with them ⁴. ASML rates the NXE:3400B's matched-machine overlay, a measure of that alignment, at 2 nm ⁴.

Finer lines need shorter light. Glass and air both absorb the shortest light in use, at 13.5 nm ⁵. So an EUV scanner works in a vacuum and uses mirrors instead of lenses, and its masks are mirrors too ⁵. Older machines use light with a wavelength more than fourteen times longer ³. Immersion scanners, one type of older machine, fill the gap between lens and wafer with water to sharpen the image ⁶.

When one exposure cannot draw a pattern finely enough, the layer is printed with two, three or four masks instead. Each extra pass costs a mask, machine time and a chance to misalign. ASML says one EUV exposure per layer cuts masks and process steps and lowers cost ².

Variants and trade-offs

Deep ultraviolet

Deep ultraviolet (DUV) light comes from gas lasers: 248 nanometers from krypton fluoride (KrF), 193 from argon fluoride (ArF), shone through air or water ³. Most of the machines sold are still DUV tools. Of the systems ASML sold in 2025, 131 were ArF immersion, 78 KrF and 16 ArF dry, all deep ultraviolet, and another 54 were older i-line tools ⁷. The i-line tools use 365 nm light from a mercury lamp, and ASML says they print features as small as 220 nm ³.

Reuters puts a DUV scanner at roughly $60 million ⁸. In DUV, ASML competes with Nikon and Canon, and it still holds above 80 percent of that market ⁸. Among DUV tools, export controls focus on immersion scanners, because without EUV a fab needs NXT:2000i-class scanners and several passes per layer to make leading-edge logic chips. Dutch export licensing covers these scanners.

Extreme ultraviolet

The 13.5 nm light comes from molten tin droplets shot from a generator ³. A laser hits each droplet twice, first with a low-intensity pulse that flattens it and then with a more powerful one that vaporizes it into plasma ³. The process repeats 50,000 times a second ³. Mirrors made by Zeiss, a German optics company, carry the light to the wafer ⁶. The largest are a meter across and smooth to within tens of picometers, a picometer being a thousandth of a nanometer ⁶.

Brighter light means more wafers an hour, and ASML ran the first 1,000-watt EUV source in April 2025 ². Its TWINSCAN NXE:3800E ships at its full 220 wafers an hour, 37 percent more than the NXE:3600D ².

High-NA EUV

High-NA scanners raise the numerical aperture (NA), a measure of how well the optics collect and focus light, from 0.33 to 0.55 ⁹. That cuts the smallest printable feature from 13 nm to 8 nm ⁹. Their optics shrink the mask image four times in one direction and eight in the other, halving the patch of wafer one exposure covers and doubling the exposures per wafer ⁹. The second-generation TWINSCAN EXE:5200B runs at 175 wafers an hour, 60 percent above the EXE:5000 ².

Reuters puts a standard EUV tool at around $200 million and a High-NA machine at $350 to $400 million, prices ASML does not publish ⁸.

Intel and TSMC have chosen differently on High-NA:

• Intel Foundry says it uses High-NA in volume production for select layers of some Intel 18A products ¹⁰. It installed the first EXE:5200B ¹¹. By September 2026 it had run more than one million wafers on High-NA tools, a count that includes tool testing and research as well as volume production ¹⁰.
• TSMC waited, and in September 2026 said it will use High-NA in high-volume manufacturing from 2030 ¹².

ASML sold four High-NA (EXE) systems in 2025, against two in 2024 ¹. In its 2025 annual report, filed in February 2026, ASML said it expected High-NA to start supporting high-volume manufacturing in 2027 ¹³. On 8 September 2026 ASML and TSMC announced a move to 12-inch photomasks to remove stitching constraints ¹². Stitching constraints are the design limits that come from printing a large chip in two halves. They aim for a pilot mask line by 2031 and 12-inch High-NA systems in production by 2033 ¹².

Who makes it

ASML's net sales were EUR 32.7 billion in 2025, at a 52.8 percent gross margin ¹. In July 2026 it raised its 2026 forecast to EUR 43 to 45 billion, at a gross margin of 54 to 56 percent ¹⁴. Its 2025 annual report lists 5,100 suppliers ¹³. Four of them make the main parts of the EUV machine:

• Zeiss SMT, Oberkochen, makes the illumination system and the six-mirror projection optics ¹⁵.
• Trumpf, Ditzingen, makes the carbon dioxide drive laser, which amplifies a few watts to 40 kilowatts ¹⁶.
• ASML San Diego, which includes the light-source maker Cymer that ASML bought in 2013, designs the source where the laser turns tin into plasma, and builds the droplet generator ¹⁷.
• VDL ETG builds the frames that suspend and position the mirrors ¹⁸.

ASML says the production capacity of Zeiss, its sole supplier of optics, limits how many lithography systems it can build ¹³.

Nikon and Canon serve narrower markets. Nikon sold 22 new chip lithography systems in the year to March 2026, in a market it sizes at 570 units for 2025 ¹⁹. Its Precision Equipment business made an operating loss in the year to March 2026 ¹⁹. Canon's alternative is nanoimprint, where the FPA-1200NZ2C stamps the pattern instead of projecting it, down to a 14 nm linewidth ²⁰. Canon delivered one in 2024 to the Texas Institute for Electronics, to be used for research and prototypes ²⁰.

Controls and China's answer

Export controls bar EUV from Chinese foundries ²¹. In September 2025 CSIS judged that EUV remained "firmly out of reach" for China despite massive state investment ²¹. For DUV scanners and other tools, the restrictions came in this order:

• Dutch national licensing of advanced DUV took effect on 1 September 2023 ²².
• A US rule published on 25 October 2023 put certain immersion scanners bound for advanced chipmaking under US export rules if they held any American content at all ²³. The rule did not apply if the country the scanners were first exported from already controlled them ²³.
• A partial license revocation by the Dutch government, disclosed by ASML on 1 January 2024, stopped shipments of NXT:2050i and NXT:2100i immersion scanners to a few Chinese customers ²⁴.
• The Netherlands widened its licensing from 7 September 2024 ²². On 15 January 2025 it announced that from 1 April 2025 the license requirement would also cover a very limited number of further goods, among them specific measuring and inspection equipment ²⁵.
• The BIS Affiliates Rule, issued by the US Bureau of Industry and Security, extended entity-list controls to affiliates owned 50 percent or more by listed entities from 29 September 2025 ²⁶. BIS then suspended it until 9 November 2026 ²⁷.
• The EU added certain Dutch controls to the EU Control List in November 2025 ¹³. ASML says this changed nothing for its immersion tools, because they already needed a Dutch license ¹³.

China's share of ASML's net system sales fell from 41 percent in 2024 to 33 percent in 2025 ⁷.

On DUV, Reuters reported in July 2026, citing one unnamed source, that Shanghai Aishengna Electronic Technology Group has started producing home-grown immersion DUV tools ²⁸. The firm was registered in August 2023 with 7 billion yuan of capital and two state shareholders, Shanghai Electric Holding and a Shanghai International Trust subsidiary ²⁸. It has no website and has taken in teams from SMEE, China's older scanner maker, and the startup Yuliangsheng ²⁸. SMEE is strongest in i-line, the coarsest kind of scanner, and even there holds about four percent of the world market ²¹.

On EUV there is less evidence. Claims of Huawei mass production in 2026 remain unverified. Reuters reported in December 2025 that a Shenzhen team of former ASML engineers had built a prototype that made extreme ultraviolet light but had printed no chip ²⁹. To print a chip, a machine also needs mirrors that carry that light to the wafer, and ASML's sole supplier of those mirrors is Zeiss ¹³.

The chokepoint

If ASML stopped shipping, no fab anywhere could add EUV scanners. Tools already in fabs would keep printing for as long as they were serviced. In its 2025 annual report ASML said about 95 percent of the systems it had sold in the previous 30 years were still in use ¹³. It guarantees service and spare parts for each platform until at least a committed date, subject to export controls ¹³. ASML itself could not quickly rebuild its production, because Zeiss makes its optics and Trumpf its drive laser.

In July 2026 ASML put its 2026 capacity at around 65 standard (low-NA) EUV scanners and said it plans to add 30 percent for 2027 ¹⁴.

For AI accelerators, EUV is the point of control, because it prints the finest layers, the ones that set how densely transistors and wires pack ⁵. TSMC expects the number of layers needing High-NA to rise as AI designs grow more complex ¹².

Each EUV layer of an AI accelerator is printed from a mask built on a blank plate. Only three companies worldwide supply those plates, and two of them are Japan's AGC and Hoya ¹. AGC says it is the only company in the world that takes an EUV blank all the way from the glass to the finished coating ².

How it works

How a photomask prints its pattern

1. 01The scanner
2. 02A mirror
3. 03The pattern
4. 04Wafer after wafer
5. 05One speck

Paused

A photomask is the stencil that lithography prints from, one for each layer of a chip. Inside the scanner, light bounces off the mask and carries its pattern down to the wafer.

1. The scanner. A photomask is the stencil that lithography prints from, one for each layer of a chip. Inside the scanner, light bounces off the mask and carries its pattern down to the wafer.
2. A mirror. No glass lets the short light now in use pass through. So the mask is a mirror, built up from about forty pairs of very thin layers laid on glass, and the light bounces off it.
3. The pattern. A dark pattern drawn on the mirror soaks up the light wherever no line should print. The light that bounces back carries the pattern of one layer.
4. Wafer after wafer. The same mask prints its layer on wafer after wafer, so one plate shapes millions of chips.
5. One speck. A speck of dust on the mask prints on every wafer, until someone finds it. The pellicle, a dust cover meant to protect the mask, is still short of production in a leading-edge fab.

Simplified. The mask is drawn face down, as it sits in the scanner. The mirror layers and the dark pattern are drawn far thicker than they are, and the light's path through the scanner's mirrors is cut to one bounce.

ASML says a chip's most complicated layers are made on EUV machines, while the rest can often be printed on older deep ultraviolet machines ³. A mask starts as a blank, a polished plate with nothing on it yet. For deep ultraviolet the blank is a window of quartz carrying a light-blocking film such as molybdenum silicide, and Shin-Etsu supplies those blanks ⁴. For EUV the blank is a mirror of about 40 molybdenum and silicon layer pairs, 7 nm to a pair, laid on glass ⁵. A dark tantalum film on top, called the absorber, will carry the pattern ⁵.

The mask shop coats the blank with a sensitive film called resist. A mask writer then draws the design into the resist with electrons. A single-beam writer flashes one shape at a time, while NuFlare's multi-beam writer for the most advanced masks controls 260,000 beams at once ⁶.

A wash removes the drawn resist. An etch then removes the blocking film or absorber wherever the resist is gone, and the rest of the resist is stripped. The plate now passes light, or reflects it, in the exact shape of one layer of the chip. On standard scanners the pattern is drawn four times larger than it will print. An inspection tool compares the plate to the design, and a repair tool fixes the stray defects it finds.

Making the plate a mirror creates its own problems:

• Mask 3D effects. Light strikes the mirror at a slant, and the absorber has height, so its edges cast small shadows that distort the printed shape. Software has to correct for the shadows in advance.
• Write precision. Every edge of the absorber has to sit within a few nanometers of where the design says.
• Particles. Anything on the mirror prints on every wafer until someone finds it.

High-NA scanners, the newest EUV machines, print finer lines with larger mirrors. To keep masks at their usual size, their mirrors shrink the pattern four times in one direction and eight times in the other ⁷. So each exposure covers half the area of a standard exposure, and a wafer takes twice as many exposures ⁷.

On 8 September 2026 ASML and TSMC announced a plan to move from the current 6-inch masks to 12-inch masks ⁸. They expect the change to raise fab productivity, lower chipmaking costs and remove stitching constraints, the design limits that come from printing a large chip in two halves ⁸. They aim to set up a 12-inch mask pilot line by 2031, so that High-NA scanners using 12-inch masks can enter advanced chip production by 2033 ⁸.

Variants and trade-offs

Blanks

AGC says it spent more than a decade meeting the blank's requirements, which include near-zero thermal expansion, perfectly smooth and flat surfaces and no particle contamination ¹. It says mass production began only in 2017 ¹.

AGC publishes no market share figure for EUV blanks. In its data book, AGC ranks itself No.2 worldwide in EUV lithography photomask blanks, based on its own fiscal 2026 estimates ⁹. Hoya says its share of the mask blank market is exceptionally high, and that customers may gradually start buying EUV blanks from more than one supplier ¹⁰.

In April 2023 AGC said its EUV blank capacity would grow by about 30 percent in 2025 ². The growth would come from a line in Fukushima, a project that METI, Japan's industry ministry, selected under a program to strengthen supply chains ². AGC also said it was aiming for more than ¥40 billion of sales in the business by 2025 ². Its EUV blank sales grew 50 percent in 2023, AGC said in December 2024 ¹. In February 2025 AGC reported that the sales reached ¥40 billion in 2024, a year ahead of the 2025 target ¹¹.

The sales then declined in 2025 and were recovering in 2026, AGC said in June 2026 ¹². In August 2026 AGC set out capacity expansions of 20 to 50 percent across EUV blanks, polishing slurry and lens materials for lithography tools ¹³. It gave no separate figure for the blanks, and mass production on the added capacity is to begin in 2028 ¹³.

Writers

An electron-beam writer draws the pattern into the resist on the blank. Multi-beam writers fire many beams at once, and Japan's NuFlare sells them for the 3 nm node ⁶.

In September 2023 Intel called Austria's IMS Nanofabrication the established industry leader in the multi-beam mask writing tools that advanced EUV requires ¹⁴. Counting all electron-beam mask writers, CSET, a research center at Georgetown University, put IMS's share of a $994 million world market at 46.6 percent in 2025 ¹⁵. NuFlare had 39.2 percent and JEOL 14.2 percent ¹⁵.

Intel agreed in September 2023 to sell roughly 10 percent of IMS to TSMC at a valuation of about $4.3 billion ¹⁴. TSMC's subsidiary TSMC Development held that 10 percent at the end of 2024, at a fair value of $432.8 million in TSMC's accounts ¹⁶. Intel sold a combined 32 percent of IMS in 2023 and still held the other 68 percent on 27 December 2025 ¹⁷.

Inspection and repair

A mask defect cuts the number of good chips on every wafer that mask prints, so fabs check masks three times: as blanks, after patterning and again in production. Actinic inspection uses 13.5 nm light, the wavelength of EUV lithography ¹⁸. In 2019 Lasertec launched the world's first actinic inspection system for patterned EUV masks, the ACTIS A150 ¹⁸. In October 2025 it launched the ACTIS A200HiT series, which it says triples the A150's inspection speed ¹⁸. Lasertec reported net sales of JPY 230,485 million in the year to June 2026 ¹⁹.

KLA sells optical inspection tools for both EUV masks and optical masks ²⁰. Zeiss makes AIMS EUV, which checks a mask in EUV light under the scanner's own imaging conditions to judge how a defect will affect printing ²¹. Zeiss calls AIMS the only system that qualifies a mask under conditions equivalent to the scanner's ²¹. Zeiss says the tool can be extended to ASML's High-NA scanner, the EXE:5000 ²¹. Zeiss also sells electron-beam repair tools that work on EUV masks ²².

Pellicles

A pellicle is a thin membrane on a frame above the mask. Particles land on it, too far out of focus to print, and the pattern below stays clean.

ASML's EUV pellicle is a membrane 13 nanometers thick that has to hold together at 500 degrees Celsius in vacuum ²³. Every photon it absorbs is light that never reaches the wafer ²³. The light crosses it twice, on the way in and on the way back off the mirror, so absorption counts double. ASML released its first EUV pellicles in 2016 and calls the pellicle one of the breakthroughs that brought EUV lithography to high-volume manufacturing ²³.

Carbon nanotube membranes are the next step, aimed at next-generation High-NA, high-output EUV scanners ²⁴. In 2020 imec, a Belgian chip research center, mounted them on masks and exposed them in an ASML NXE:3300 scanner ²⁵. The membranes passed up to 97 percent of the light in a single crossing, and imec found their effect on imaging low and correctable ²⁵.

Mitsui Chemicals began commercial production of silicon-based EUV pellicles under an ASML license in 2021 ²⁴. In 2024 it said it would build a carbon nanotube membrane plant at Iwakuni-Ohtake, tentatively due to finish in December 2025 ²⁴. The membranes are designed to pass 92 percent or more of the light and to withstand exposure power above 1 kW ²⁴.

Cost and design economics

In July 2022 SemiAnalysis put mask sets above $1 million at 28 nm and above $10 million at 7 nm ²⁶. It expected 3 nm mask sets to reach the $40 million range ²⁶. Its May 2026 primer still puts a leading-edge mask set at $40 million ²⁷. The same primer puts a single respin, remaking a chip after a design flaw, at $50 million to $100 million at leading-edge nodes ²⁷.

Mask costs restrict which firms can use a node. SemiAnalysis wrote that at 5 nm and 3 nm, only firms with large wafer volume see the cost per transistor fall ²⁶. It wrote that more companies will lack the volume to spread the fixed cost of mask sets ²⁶. It expected failed chip designs to show up first among AI chip startups, which work on much tighter budgets ²⁶.

Who makes it

Mask making splits between chipmakers that make masks for their own use and independent merchant firms that sell to them and others ²⁸. Photronics says that chipmakers' own shops once supplied most of the market, and that production has more recently tended to move toward the independents ²⁸.

Photronics calls itself a leading worldwide maker of masks for chips and flat panel displays ²⁹. It had $849.3 million of revenue in fiscal 2025, $615.1 million of it from chip masks ²⁹. The competitors it names in chip and display masks include Dai Nippon Printing, Hoya, Tekscend Photomask and two Chinese firms, Shenzhen Newway Photomask and Shenzhen Qingyi Photomask ²⁸. It also competes with chipmakers' own mask shops ²⁸.

SMIC, a Chinese foundry, runs two in-house mask shops in Shanghai, for g-line, i-line, DUV and ArF steppers and scanners ³⁰. Photronics began operating two mask plants in China, in Hefei and Xiamen, in 2019 ²⁸. Its chip mask business in Xiamen is a joint venture in which Dai Nippon Printing holds 49.99 percent ²⁸. No Chinese firm appears in CSET's 2025 market shares for electron-beam mask writers ¹⁵.

The chokepoint

Mask blanks are a small, highly concentrated business. In 2019 Lasertec launched the first tool that inspects patterned EUV masks in EUV light ¹⁸.

Pellicles already work in high-volume EUV manufacturing ²³. But ASML says no material is completely transparent to EUV light, so any pellicle in the light's path costs customers productivity ²³. In 2024 Mitsui Chemicals said it would set up production of carbon nanotube membranes for next-generation High-NA, high-output EUV scanners ²⁴.

Applied Materials and Lam Research are the two largest deposition and etch suppliers. Applied Materials booked $28.4 billion of revenue in fiscal 2025 ¹. Lam Research booked $23.2 billion in fiscal 2026 ².

How it works

One round of deposition and etch

1. 01The wafer
2. 02Deposit
3. 03Coat
4. 04Expose
5. 05Develop
6. 06Etch
7. 07Strip
8. 08Repeat

Paused

A slice through one spot on a wafer, magnified until its layers show.

1. The wafer. A slice through one spot on a wafer, magnified until its layers show.
2. Deposit. A film a few atoms thick is laid over the whole wafer.
3. Coat. A light-sensitive coating, the resist, is spun on top.
4. Expose. Light shines through a stencil and changes the resist wherever it lands.
5. Develop. A wash removes the resist the light reached, leaving the stencil’s pattern.
6. Etch. A plasma cuts straight down through the film wherever the resist is gone.
7. Strip. The leftover resist is removed. The pattern now sits in the film.
8. Repeat. Insulator fills the gaps and the next layer goes on. A chip takes more than a thousand of these rounds.

Simplified cross-section. The layers are drawn much thicker than they are.

Most etch steps, and many deposition steps, happen in a vacuum chamber that holds one wafer at a time. A pump empties the chamber of air, and a measured flow of gas comes in. A radio-frequency field, an electric field that reverses millions of times a second, turns the gas into a plasma. The field splits the gas into charged ions and into neutral fragments called radicals, which are more reactive than whole molecules ⁵. Batch furnaces such as Tokyo Electron's TELINDY PLUS instead heat as many as 125 wafers at once, usually without plasma, for oxidation, low-pressure chemical vapor deposition and some atomic layer deposition ⁶.

For deposition, the gas carries the material the film will be made of. The molecules, or the radicals a plasma splits from them, land on the wafer and stick. The film builds from the bottom up, a few atoms at a time.

To coat the floor of a deep hole as thickly as its rim, the machine can work in cycles, a method called atomic layer deposition. First one gas settles in a single layer on every surface, and the pump removes the rest. Then a second gas reacts with that layer and nothing else, and the pump empties the chamber again. Each cycle adds a fraction of a layer of atoms wherever the gas reached, so the film grows as evenly on a hole's walls and floor as on its rim ⁷.

For etch, the gas attacks one material and leaves the one beside it. Wherever the photoresist pattern covers the wafer, nothing happens. Wherever it does not, the radicals react with the surface and turn it into a gas, which the pump carries away. A second field pulls the ions straight down at the wafer, so the etch cuts vertically and a narrow hole keeps its width as it deepens ⁵. When the etch reaches the material underneath, which the gas was chosen not to touch, it slows almost to a stop, and the tool ends the step.

Deposition and etch chambers are separate products built from similar vacuum, gas and radio-frequency parts, and the export controls describe each tool by the process it is designed to run ⁷.

Accenture and the Global Semiconductor Alliance estimated in 2020 that a part-finished chip can cross international borders 70 or more times on its way to the end customer ³. The Semiconductor Industry Association repeated the figure in 2025 ³.

Variants and trade-offs

Deposition families

The market sizes and leading shares below are 2025 figures from Georgetown University's Center for Security and Emerging Technology (CSET), based on data from the research firm TechInsights. CSET puts the deposition tool market at $26.2 billion ⁸. It puts the dry etch market at $21.9 billion ⁹.

• Physical vapor deposition (PVD), which knocks atoms off a solid target and lands them on the wafer, was a $4.9 billion market in 2025 ¹⁰. Applied Materials held 82.4 percent of it and China's Naura 14.7 percent ¹⁰.
• Chemical vapor deposition (CVD), which reacts gases at the wafer surface to grow a film, was an $11.2 billion market in 2025, led by Applied Materials at 47 percent ¹¹. The plasma-enhanced version (PECVD) runs cooler and made up most of it, $7.5 billion ¹².
• Atomic layer deposition (ALD) lays down less than one atomic layer at a time, so it coats vertical walls as evenly as horizontal floors. US regulators say that even coating makes it important for building 3D structures, such as 3D DRAM, 3D NAND, and the FinFET and gate-all-around transistors in logic chips ⁷. ASM International leads it with 54.5 percent of a $4.1 billion market in 2025 ¹³.
• Epitaxy grows layers that line up with the crystal beneath them, using high-temperature CVD tools ¹⁴. Electroplating deposits the copper used for wiring across the wafer ¹⁵.

Etch families

• Conductor etch, which cuts gates, metals and silicon, was a $12.2 billion market in 2025, led by Lam at 51.2 percent ¹⁶.
• Dielectric etch, which cuts the insulating oxides and nitrides between them, was an $8.7 billion market in 2025, led by Tokyo Electron at 55.9 percent ¹⁷.
• High-aspect-ratio etch cuts the deep, narrow channels that let 3D NAND stack layers of memory cells ⁴. Lam says slight departures from a channel's intended shape can hurt yield ⁴. Lam runs this etch well below 0 degrees Celsius ⁴. It says its Cryo 3.0 technology keeps the deviation in a channel's width from top to bottom under 0.1 percent, in channels up to 10 microns deep ⁴.

AI hardware needs sideways cuts, deeper holes and a second stack of metal wiring on the back of the wafer.

• Gate-all-around transistors need highly selective isotropic etch, which cuts sideways ⁷. The US Bureau of Industry and Security (BIS) controls isotropic dry etch tools that remove silicon-germanium at least 100 times faster than silicon, a selectivity of 100:1 or more ⁷.
• HBM (high-bandwidth memory) needs holes etched straight through the silicon, called through-silicon vias (TSVs), so chips can be stacked and wired ¹⁸. BIS controls the tools that etch these holes at aspect ratios (depth to width) of 10:1 or more and at rates above 7 microns a minute ¹⁸.
• Backside power delivery moves the wires that carry power to the back of the wafer ¹⁹. Applied Materials expects it to add another $1 billion per 100,000 wafer starts a month to the wiring market it serves ²⁰.

Who makes it

The industry association SEMI put world sales of chipmaking equipment at $135.1 billion in 2025, up 15 percent from $117.1 billion ²². Sales of wafer processing equipment, the category that includes deposition and etch tools, rose 12 percent ²².

No one firm dominates deposition and etch the way ASML dominates lithography. Tokyo Electron's own results presentation gives it 23 percent of dry etch, 27 percent of deposition systems (furnace, ALD and low-pressure CVD tools) and 15 percent of ALD in 2025 ²¹. The same presentation gives it 91 percent of coater/developers in 2025 ²¹. These machines coat wafers with photoresist and develop the pattern after lithography.

ASM International, the atomic layer deposition specialist, reached a record EUR 3.2 billion of revenue in 2025 as customers built 2 nm gate-all-around capacity ²³. Molybdenum ALD, a new use of its tools that deposits the metal molybdenum, entered volume production that year ²³.

China and the controls

China is the tool vendors' largest market, and Chinese toolmakers have gained share since 2019 ²⁴. It bought $49.3 billion of equipment in 2025, half a percent less than in 2024, and remained the biggest single market ²². Taiwan's spending rose 90 percent to $31.5 billion ²². South Korea's rose 26 percent to $25.8 billion ²². China still takes a large share of every major vendor's sales.

• Tokyo Electron: 34.1 percent of sales in the year to March 2026, down from 41.7 percent ²¹.
• Lam Research: 26 percent in the June 2026 quarter, behind Taiwan at 27 percent ².
• Applied Materials: 28 percent in the third fiscal quarter of 2026, down from 35 percent ²⁵.
• ASM International: more than 30 percent of 2025 revenue ²³.

Between 2019 and 2024 China-based suppliers went from 2 to 7 percent of deposition and from under 3 to almost 9 percent of etch and clean ²⁴. In ALD they gained no share and held less than 1 percent in 2024 ²⁴.

CSET's newer analysis of TechInsights data, published in July 2026, puts them at 9.8 percent of deposition in 2025 ⁸. They held 10.1 percent of etch and clean that year ²⁶. In dry etch alone their share was 12.4 percent ⁹. In ALD they held 2.6 percent in 2025, most of it from Piotech ¹³.

The Chinese toolmaker AMEC alone held 12.4 percent of dielectric etch in 2025 ¹⁷. Its revenue was RMB 12.385 billion that year, up 36.6 percent, and it spent RMB 3.744 billion on research, 30.2 percent of sales ²⁷.

The United States tightened its export controls at least five times between 2022 and 2025.

• October 2022. The 7 October interim final rule required a license for certain chipmaking equipment, and for some activities by US persons that support the making of certain chips in China ²⁸. It also widened foreign-produced item rules for 28 Chinese entities already on the Entity List, the US list of foreign firms that exporters need a license to supply ²⁸.
• October 2023. The October rule, effective 17 November, rewrote the equipment entries ⁷. It added sideways (isotropic) and vertical (anisotropic) dry etch (ECCN 3B001.c.1), spatial ALD (3B001.d.9), low-fluorine tungsten ALD and CVD (3B001.d.10) and carbon hard mask PECVD (3B001.d.5) ⁷.
• December 2024. BIS controlled 24 more types of equipment and three types of software, and added 140 entities to the Entity List ²⁹. The new equipment entries include TSV etch, and deposition into features with aspect ratios above 200:1 ¹⁸. BIS also wrote a foreign direct product rule that reaches some tools built outside the United States ²⁹. The rule largely exempts foreign-made tools exported by firms located in Japan, the Netherlands and the 31 other countries it lists, whose governments can control these tools themselves ¹⁸. Japan added advanced chipmaking equipment to its control list on 23 July 2023 ¹⁸.
• September 2025. BIS removed the Chinese units of Samsung and SK hynix, and Intel Semiconductor (Dalian), from the Validated End-User program, effective 31 December 2025 ³⁰. From that date, US tools bound for them need a license ³⁰. BIS estimated that the change would add 1,000 license applications a year ³⁰.
• September 2025. The Affiliates Rule extended Entity List restrictions to any company at least 50 percent owned by a listed entity ³¹. BIS then suspended it until 9 November 2026 ³².

The rules apply to the toolmakers as well as to their customers. Applied Materials took a $253 million charge to settle an export controls compliance matter with BIS ²⁵.

Of the tools in the chart below, China-based suppliers have their largest share in dry stripping, which clears leftover photoresist off the wafer and was a $314.6 million market in 2025 ³³. Kokusai held 35.7 percent of it, Mattson Technology 22.6 percent and Naura 8.3 percent ³³. Mattson is a US-based firm that Beijing E-Town bought in 2016 ²⁴.

The chokepoint

Deposition and etch tools are a chokepoint, but a weaker one than lithography. Most deposition and etch steps have three or four credible vendors. Atomic layer deposition has at least five ¹³. The December 2024 rule targets advanced atomic layer deposition tools and the extremely deep, narrow holes that HBM and 3D memory need ¹⁸.

Process control tools, the machines that measure and inspect wafers, were a $15.7 billion market in 2025 ¹. KLA puts the whole wafer equipment market, including advanced packaging, at about $120 billion that year ².

CSET's count for 2025, built on TechInsights data, puts KLA at 56.8 percent, about five times Applied Materials' 11.2 percent ¹. At its March 2026 investor day KLA cited Gartner's figures for 2024, which put its share at 56.5 percent, 6.5 times its nearest competitor ³. In April 2026 KLA said its 2025 share was about 7 times the nearest competitor's ⁴. The figures use different data and years, so KLA's lead over the next firm ranges from about 5 to about 7 times.

How it works

An inspection tool sweeps a beam of light across the wafer, photographs it, and compares the image of each chip with the image of its neighbors. The chips on a wafer are meant to be identical, so anything that shows in one and not the others is a defect. The tool records where each defect is. For faults too small for light to show, a second tool scans a beam of electrons across a small patch and builds a picture from the electrons that bounce back.

A metrology tool measures known shapes. It shines light on a test pattern printed beside the circuits and works out from the scattered light how wide the lines are and how thick the film is. It also reads marks printed in this layer and the last to measure how far the two are out of line, which chipmakers call overlay.

The fab pays for all this to protect yield, the share of chips on a wafer that work. A wafer loses value two ways: whole regions ruined by mishandling, misalignment or over-etching, and single circuits killed by stray material or an airborne particle ⁵.

A bigger chip is a bigger target for the second kind, and the loss grows faster than the area. Chipmakers call each chip on a wafer a die. In the standard formula, die yield is (1 + D0A/a) to the power minus a. Here D0 is defects per square centimeter, A is die area, and a is a clustering constant of 3 to 4 that says how much defects bunch together. At a defect density of 0.8 per square centimeter, with a set to 3, a 1 square centimeter die yields 49.2 percent and a 2 by 2 centimeter die 11.3 percent ⁵. Because the bigger die yields less and fits fewer times on a wafer, it costs 20.1 times as much as the small one ⁵.

By the same formula, an 8 square centimeter die, about as much as one exposure can print, yields about 49 percent at 0.10 defects per square centimeter, with a set to 3 ⁵. Halving the defect density to 0.05 lifts that yield to about 69 percent ⁵. Engineers move a fab from the first figure to the second by finding the process step that is losing dies and fixing it, work called yield learning.

Those percentages are the share of dies with no killer defect. A chip built from many identical blocks can carry spares and switch off a faulty block ⁵. Nvidia's full H100 design has 144 of its main computing blocks, called streaming multiprocessors, and the SXM5 version it ships has 132 turned on ⁶. So the share of dies that can be sold is higher than the formula gives. But the formula shows how fast flawless dies get scarce as chips grow.

Why big chips lose more to defects

1. 01Specks land
2. 02Small chips
3. 03AI-size chips
4. 04Half the specks

Paused

Specks of dust and tiny flaws land at random on every wafer.

1. Specks land. Specks of dust and tiny flaws land at random on every wafer.
2. Small chips. Cut into small chips, almost every chip misses every speck.
3. AI-size chips. An AI chip covers eight times the area, so about half of them catch a speck and fail.
4. Half the specks. Halve the specks and about seven in ten AI chips work. Finding defects pays most on the biggest chips.

Simulated 300 mm wafer: 68 specks, 0.10 per square centimeter, placed at random in loose clusters. The share of flawless chips follows the formula above with a clustering constant of 3.

Variants and trade-offs

The tools trade sensitivity against speed. All the market sizes and shares below are CSET's, for 2025 ¹.

• Defect inspection scans a whole wafer with light or electrons and compares each die against its neighbors. It is by far the largest family, at $6.7 billion, and KLA held 85.9 percent of it. ASML's HMI eScan 1100 runs 25 electron beams at once, up to 15 times the throughput of single-beam inspection tools, and finds patterning defects down to 7 nm ⁷.
• Film and shape metrology measures how thick each film is and how flat the wafer sits, without cutting it open. In this $2.6 billion family KLA held 45.6 percent, Nova 24.6 and Onto Innovation 10.9. Onto paid about $720 million in August 2026 for 27 percent of the Japanese X-ray tool maker Rigaku ⁸.
• Mask inspection and repair has its own tools, because a defect on a mask, the stencil the circuit pattern is printed from, repeats on every die. This $2.2 billion family is one of two where KLA has a close rival. KLA held 45.9 percent, Lasertec 42 and Zeiss 10.1. Lasertec also makes actinic inspection tools, which check EUV masks with the same 13.5 nm light that prints them ⁹. Lasertec calls its ACTIS A150 the world's first EUV patterned mask inspection system ⁹. KLA's own actinic mask inspection tool was still at an early demo stage at its March 2026 investor day ³.
• Overlay metrology measures whether this layer sits on the one below. Its $991.4 million market was split almost evenly between KLA at 51.5 percent and ASML at 47.9.
• Critical dimension metrology, also called line-width measurement, measures how wide a printed feature came out. It is the one family Japan leads. Hitachi held 71.9 percent of this $1.2 billion market and Applied Materials 27.5.
• Electron-beam metrology resolves detail too fine for light. Applied Materials led this $1.3 billion family at 45.1 percent, with ASML at 35.6 and KLA at 18.8.

Who makes it

KLA says its share grew 3.6 percentage points from 2021 to 2025 ⁴. It says it gained share again in 2025 across mask, optical wafer and e-beam inspection ⁴. Its revenue for fiscal 2026, the year to June 2026, was $13.579 billion, up from $12.156 billion in fiscal 2025 ¹⁰.

The rest are specialists, and none holds more than 11.2 percent, by CSET's count for 2025 ¹.

• Applied Materials is the largest of them. It sells e-beam defect review tools, CD-SEMs (electron microscopes that measure line width) and e-beam metrology tools next to the deposition and etch tools that create the defects.
• Lasertec holds 6.4 percent, almost all of it mask inspection. Hitachi High-Tech holds 6.2 percent, most of it from CD-SEMs. ASML holds 5.9 percent through YieldStar overlay and HMI e-beam metrology.
• Nova holds 4.3 percent, through film metrology, and took $880.6 million of revenue in 2025 ¹¹.
• Onto Innovation holds 2.6 percent on $1,005.3 million of 2025 revenue ¹². Camtek holds 1.6 percent on $496.1 million of 2025 revenue ¹³.

KLA's patterning line, which includes several metrology products and mask inspection, grew 61 percent year on year in the June 2026 quarter ². In that quarter Taiwan took 31 percent of KLA's revenue and China 26 percent ².

KLA says process control's share of fab spending is still rising ⁴. In memory chips, KLA credits the rise to higher performance specifications, less redundancy (fewer spare circuits) and more logic content in devices built for high-performance computing ⁴.

KLA's systems analyze data with AI and also filter out noise ⁴. In April 2026 KLA said it had added AI to every product line over the previous five years ⁴.

Packaging, AI and China

KLA says the AI build-out is making advanced packaging, and the process control it needs, more important ². KLA became the largest supplier of process control tools for advanced wafer-level packaging in 2025, adding 14 percentage points of share ⁴. It expects about $1.1 billion of packaging process control revenue in 2026, up more than 70 percent ². Onto signed a volume purchase agreement estimated at over $240 million with an HBM maker for 2D inspection and 3D bump metrology through 2027 ¹².

Chinese makers are still small in process control, but one of them is growing fast. CSET's count, built on TechInsights data, puts all Chinese firms at 0.7 percent of the market in 2025 ¹. Skyverse (Shenzhen Zhongke Feice), a maker of wafer inspection and metrology tools, reported 2.05 billion yuan of revenue in 2025, about $285 million ¹⁴. That was up 48.75 percent on 2024 and more than double its 2023 revenue ¹⁴. Skyverse's revenue alone is about 1.8 percent of CSET's market, more than twice CSET's figure for all Chinese firms, so the CSET count may miss some domestic sales ¹. In its 2025 annual report Skyverse says Chinese makers still hold a low share of China's market for these tools and that KLA holds the largest share of it ¹⁴.

By CSET's 2025 count, Chinese firms held 0.6 percent of defect inspection tools ¹⁵. They held 0.4 percent of line-width measurement tools in 2025 ¹⁶. In film and shape metrology they held 2 percent in 2025, all of it from Raintree Scientific Instruments, or RSIC ¹⁷. They held no share of mask inspection and repair tools in 2025 ¹⁸. Nor did they hold any share that year of the tools that inspect wafers during advanced packaging ¹⁹.

In October 2022 the US began requiring a license for any US-made item, process control tools included, bound for certain Chinese fabs ²⁰. The rule covered fabs that made logic chips at 16/14 nm or below, NAND memory with 128 or more layers, or DRAM at 18 nm half-pitch or below ²⁰.

A December 2024 rule added specific process control tools to the export control list. It controls tools for defect inspection and measurement of patterned 300 mm wafers if they can find defects of 21 nm or smaller ²¹. They must do this using light with a wavelength below 400 nm, an electron beam resolving 1.65 nm, a cold field emission source, or two or more beams ²¹. The same rule controls overlay metrology accurate to 0.5 nm or better if the tool is built into the track (the machine that coats and develops the light-sensitive resist) or can switch wavelengths quickly ²¹. It also controls stand-alone wafer shape metrology that feeds corrections to immersion or EUV scanners ²¹. A separate new entry, 3B994, covers optical film and line-width metrology for 300 mm wafers with software for measuring non-planar transistors ²¹.

BIS, the US Commerce Department bureau that wrote the rule, placed these tools in new entries for items it says also have legitimate uses in older chipmaking ²¹. So they carry narrower license requirements than tools built only for advanced chips ²¹. A new foreign direct product rule extends US jurisdiction to specified foreign-made chipmaking tools bound for Macau or for a Country Group D:5 destination such as China ²².

The chokepoint

One firm, KLA, held more than half the process control market in 2025. Several firms can build a good film metrology tool, but KLA leads most kinds of process control tool, and it says its share grew from 2021 to 2025. A fab that can buy scanners and etchers but not sensitive inspection tools finds fewer of the defects that lower its yield, so its yield rises more slowly.

Nvidia's Blackwell GPU holds 208 billion switches on two dies, each die the largest a lithography machine can print in one shot ¹. Every switch has to turn on fully, turn off completely, and keep doing it for years. Making the switches is called the front end of line. Wiring them together is the back end of line.

How it works

Why the gate wraps around the channel

1. 01Inside a chip
2. 02On
3. 03Off, leaking
4. 04Fin
5. 05All around

Paused

An AI chip does all its work with transistors, tiny switches built into the silicon: 208 billion of them in one Nvidia Blackwell GPU. Making the switches is the front end of the factory; wiring them together comes after.

1. Inside a chip. An AI chip does all its work with transistors, tiny switches built into the silicon: 208 billion of them in one Nvidia Blackwell GPU. Making the switches is the front end of the factory; wiring them together comes after.
2. On. Each one is a switch. Seen end on, current flows through a strip of silicon, the channel, and the gate sits on top.
3. Off, leaking. Switching off, the gate squeezes the flow shut, but only near itself. In a tiny transistor, current still leaks through the part it cannot reach.
4. Fin. Stand the channel on edge as a fin, and the gate covers three sides. Much less gets through.
5. All around. Split it into thin sheets and wrap the gate around every side, and it shuts tight. That lets the switches keep shrinking, and smaller switches, packed tighter, are what make each new chip faster.

Simplified. The channel is seen end on, cut across the gate, with current drawn as points of light. Not to scale.

The front end builds the transistors in a fixed order. First it marks where each transistor will sit and fires atoms of boron or phosphorus into the silicon there. This step, called ion implantation, makes those patches conduct the way the design needs.

Next it shapes the channel. In a FinFET, the older design, the fab etches the silicon into thin fins that stand up from the wafer. The gate then goes over the top and both sides of each fin, three sides instead of one.

In a gate-all-around transistor, the fab instead grows alternating layers of silicon and silicon-germanium and cuts the stack into a narrow bar. It then dissolves the silicon-germanium away, leaving thin silicon sheets held at their ends like shelves. It coats every sheet with an insulating film a few atoms thick, so the gate can control the channel without touching it. Gate metal then fills the gaps above, below and beside each sheet, covering all four sides. Last come the contacts, small metal plugs down to the two ends of the channel and to the gate, ready for the wiring layers above.

Each of those steps is a separate deposition, etch or implant. They have to run in exact order, because later layers cover earlier ones. Once gate metal surrounds a sheet, the insulator can no longer go between them.

Current leaks two ways, straight through the gate insulator and along the channel from end to end while the gate is off. The second is called short-channel leakage, and wrapping the gate around the channel reduces it. Three fixes deal with the two leaks:

• Better insulator. A thicker hafnium-based film, paired with a metal gate, lets fewer electrons slip straight through yet controls the channel as tightly as before. Intel replaced the silicon dioxide insulator with it at 45 nm in 2007 ². It said the new film cut leakage through the insulator more than tenfold and, with the metal gate, leakage along the channel more than fivefold ².
• More gate. Fins and nanosheets wrap gate metal around more sides of the channel.
• Thinner channel. The fab thins the silicon until no current can flow where the gate cannot reach it.

Variants and trade-offs

Planar and FinFET

A planar transistor lays the gate on one side of a flat channel. As the channel shortens, the gate loses control of it. A fin stands the channel on edge so the gate covers three sides. But each fin adds a fixed amount of current, so a designer who needs more current has to add a whole fin.

Gate-all-around nanosheets

A nanosheet transistor lays the channel flat again, stacks two to four thin sheets and wraps gate metal around each one. The sheets can be drawn at different widths, so current can be set in finer steps. TSMC sells this as NanoFlex, which lets designers mix short logic cells for small area with tall cells for performance ³.

TSMC's N2, its first nanosheet node, entered volume production in the fourth quarter of 2025 ⁴. TSMC rates the follow-on N2P at 18 percent more speed at the same power, 36 percent less power at the same speed, and 1.2 times the logic density of its earlier N3E ⁵. Intel's version, called RibbonFET, shipped on its 18A process ⁶. An improved version, 18A-P, adds another 9 percent performance at the same power ⁶. Samsung began initial production of its 3 nm gate-all-around process in June 2022, more than three years before TSMC's N2 ⁷.

Those numbers are the foundries' own claims until someone measures the silicon. Each foundry picks its own baseline, and none publishes a density figure that can be compared with a rival's.

Backside power delivery

In a conventional chip, power and signal share one stack of copper wiring above the transistors, where wide power rails crowd out the signal wires. With backside power, the fab grinds the wafer thin and builds a second network for power underneath it.

Intel shipped backside power first, as PowerVia on 18A ⁶. It cut routed area by 11 percent and dynamic voltage droop tenfold ⁶. Droop is the sag in supply voltage when a block of logic switches on at once. TSMC's Super Power Rail connects the backside network directly to each transistor's source and drain, the two ends of its channel. Against N2P, TSMC rates A16, which uses Super Power Rail, at 8 to 10 percent more speed, 15 to 20 percent less power and up to 1.10 times the chip density ⁵.

TSMC said in April 2026 that two more processes, A13 and A12, are scheduled to enter production in 2029 ⁸. A13 is a direct shrink of A14 with 6 percent area savings, and A12 adds Super Power Rail to the A14 platform ⁸.

CFET and what comes after

A basic logic circuit needs two transistors that switch on opposite signals, and in production chips the two sit side by side. Complementary field-effect transistors, or CFETs, stack the two on top of each other ⁹. The research institute imec sees them as an attractive design for logic nodes beyond 1 nm ⁹.

The back end of line

Wiring has become as hard to make as the transistor. Copper seeps into the insulator around it, so every wire needs a barrier, a liner and a cap ¹⁰. As the most critical wiring levels drop below a 20 nm pitch, those extra layers take a large share of the wire's width ¹⁰. Pitch is the distance from the center of one wire to the center of the next. Two metals are moving into those narrow levels.

• Ruthenium shows promise for use without a barrier, which would keep the wire's resistance low ¹⁰. imec has demonstrated ruthenium lines at a 16 nm pitch ¹¹.
• Molybdenum conducts worse than copper in bulk, with a resistivity of 5.3 microhm-cm against copper's 1.68 ¹². But in a thin film it beats tungsten by up to 30 percent and needs no barrier either, so chipmakers are putting it into some contacts and local wiring layers ¹².

Who makes it

TSMC, Intel and Samsung build gate-all-around nodes with extreme-ultraviolet (EUV) lithography. China's SMIC builds 7 nm-class nodes without it ¹³. In July 2025 Rapidus, a state-backed newcomer in Japan, said it had started making 2 nm prototypes at its plant in Chitose, Hokkaido, and would begin mass production in 2027 ¹⁴. By June 2026 it had raised 424.95 billion yen in equity, the latest 150 billion yen from a state agency ¹⁵. It has also received government research subsidies since fiscal 2022 ¹⁵.

A node's name, such as 7 nm, does not measure any feature on the chip. SMIC's N+3, its third-generation 7 nm process, sets its narrowest wires 32.5 nm apart, tighter than Intel 18A's 36 nm, though SemiAnalysis called that comparison an incomplete, cherry-picked metric ¹³. It packs 113.4 million transistors per square millimeter, against 107.7 for TSMC's N6 ¹³.

AI accelerators have usually trailed the leading edge, because a die as large as theirs comes out working reliably only on a process that has run for years. Blackwell uses a custom TSMC 4NP process ¹. AMD's MI455X, launched on 23 July 2026, lists TSMC 2 nm and 3 nm silicon ¹⁶. It spreads its compute across eight separate dies ¹⁷.

SRAM, the fast memory on the logic die, is the part whose failure to shrink hurts AI chips most. TSMC claims 22 percent more SRAM density from N3E to N2 ¹⁸. But the gain comes mostly from the circuits around the memory array, and the cell that holds one bit shrinks little or not at all ¹⁸. See Memory and HBM.

The chokepoint

TSMC, Intel and Samsung do not sell their process recipes, which set the steps, their order and the tools for each. In September 2024 the United States put a worldwide license requirement on the know-how for building gate-all-around transistors, with an exception for countries that impose matching controls ¹⁹.

China launched its third National Integrated Circuit Fund in May 2024 with 344 billion yuan, about $47 billion ²⁰. But China cannot buy EUV scanners.

A Shanghai state firm began building domestic immersion scanners in 2026 and planned about five that year and roughly 20 in 2027 ²¹. Those are deep-ultraviolet machines, a generation behind EUV. SMIC gets fine features out of them by printing its tightest layers in several passes ¹³. That many scanners keep those lines running but come nowhere near replacing ASML, the Dutch scanner maker.

Domestic EUV is further off. China has announced $43 billion to develop it ²². In September 2025 the Center for Strategic and International Studies (CSIS) judged that EUV remains firmly out of reach despite massive state investment ²².

See Lithography and Geopolitics.

TSMC calls a plant a GIGAFAB once it can run more than 100,000 wafers a month, each a 300 mm disc, twelve inches across ¹. It operates six of them, and every one is in Taiwan ².

How it works

Inside, a chip is built up in layers, and the same loop of steps repeats for each one. Wafers travel in a lot, a batch of 25 in a sealed pod called a FOUP that only a machine opens. An overhead track carries the pod from tool to tool.

At each tool a robot lifts one wafer out and the tool does its one job: depositing a film, printing a pattern, etching it, cleaning it or measuring it. Then the robot puts the wafer back. The pod moves on to the next tool, often across the building. When a layer is finished, the loop starts again with the next one. A chip takes hundreds of those visits, so a wafer spends months inside.

The pod keeps the wafer clean for all of that time because the wafer never meets the room's air. That air is also filtered until it carries almost no dust.

Every design in the building runs on the same tools because each tool is set by a recipe, the list of gases, temperatures and times for one step. A foundry offers each customer the same list of recipes on shared machines. The tools run day and night, because an idle tool earns nothing. The finished wafer is tested (see Test and assembly), then cut and packaged.

TSMC, founded in 1987, pioneered the pure-play model, in which a foundry makes only its customers' products ³. In 2023 the Boston Consulting Group (BCG) estimated that a new fab for chips at 2 nm and below, completed in 2026, would cost $35 to $43 billion to own over ten years ⁴. That is 33 to 66 percent above 2023 costs ⁴. In March 2026 the Semiconductor Industry Association (SIA) told the US Senate that building and equipping a leading-edge fab takes as much as $20 to $25 billion of capital ⁵.

Together, the plants TSMC and its subsidiaries run had capacity for more than 17 million wafers a year in 2025, counted as if each were the standard 12-inch size ². The six largest plants, called gigafabs, had a combined capacity of more than 13 million ¹. The other plants are five smaller fabs in Taiwan, two in China, two in the United States and one in Japan ².

Variants and trade-offs

Pure-play foundries

TSMC and UMC, both based in Taiwan, make chips only for other companies. Chips at 7 nm and below, meaning the newest processes, were 77 percent of TSMC's wafer revenue in the second quarter of 2026 ⁶. That share split into 33 percent at 5 nm, 30 at 3 nm, 11 at 7 nm and 3 at 2 nm ⁶. TSMC's revenue for the quarter was $40.20 billion, at a 67.7 percent gross margin ⁶.

Integrated device makers turned foundry

Intel and Samsung design and sell their own chips and rent out capacity too. Renting out capacity is harder for them, because customers dislike handing designs to a competitor and the company's own products take the best capacity. Intel Foundry reported $5.8 billion of segment revenue in the second quarter of 2026 and an operating loss of $2.089 billion ⁷. Only $293 million of that revenue came from outside customers ⁸. Intel says substantially all of its foundry business still makes Intel's own products ⁸.

National champions

China's SMIC and Hua Hong and Japan's Rapidus have government backing. SMIC's revenue rose 16.2 percent to $9.327 billion in 2025, at a 21 percent gross margin ⁹. Its lines ran 93.5 percent full, on monthly capacity above a million wafers counted in the smaller 8-inch size ⁹. SMIC cannot buy an EUV scanner, yet it makes 7 nm-class chips on its N+2 and N+3 processes by printing the tightest layers in several passes on older deep-ultraviolet scanners ¹⁰.

Georgetown University's Center for Security and Emerging Technology (CSET) reported in June 2024 that Huawei's Ascend 910B AI chip is believed to be made on N+2 ¹¹. It also reported that SMIC's limited 7 nm capacity forced Huawei to choose between its most advanced phone chips and its AI chips ¹¹. But the research firm SemiAnalysis judged in April 2025 that most 910B and 910C chips were made on TSMC's 7 nm process, from wafers Huawei bought through another company ¹².

In February 2026 Rapidus raised 267.6 billion yen from the Japanese government and 32 companies to reach 2 nm mass production by 2027 ¹³.

Mature-node capacity

Most wafers come off older lines. These make power devices, analog chips and microcontrollers, and they compete on price. In January 2025 the industry association SEMI forecast that foundry capacity at all nodes would rise from 11.3 million wafers a month in 2024 to a record 12.6 million in 2025, counted in the 8-inch size ¹⁴. Its June 2024 forecast had credited much of that growth to Intel's new foundry business and China's expansion ¹⁵. But in July 2025 Intel scaled back its own fab plans, saying it would no longer go ahead with planned projects in Germany and Poland and would slow construction in Ohio ¹⁶.

Capacity and cost

In March 2025 TSMC added $100 billion to the $65 billion it had already committed in Phoenix, for three more fabs, two packaging plants and an R&D center ¹⁷. In July 2026 it added another $100 billion for four more fabs at 2 nm or below, taking its total investment in Arizona to $265 billion across 12 facilities ¹⁸.

Some customers pay TSMC in advance to hold capacity at its fabs ¹⁹. These deposits stood at NT$189.9 billion at the end of 2025, down from NT$291.1 billion a year earlier ¹⁹. In 2025 the four largest AI chip designers used around 90 percent of the world's CoWoS packaging capacity and HBM memory supply, against only 12 percent of advanced logic production ²⁰. See Advanced packaging.

Who makes it

The US government owns part of Intel. In August 2025 the government bought 433.3 million newly issued Intel shares at $20.47 each, or $8.9 billion in all, for a 9.9 percent stake ²¹. It paid with $5.7 billion of CHIPS Act grants that Intel had not yet received and $3.2 billion from the Secure Enclave program ²¹. Announcing the deal, Intel's chief executive, Lip-Bu Tan, called Intel the only semiconductor company that both develops and manufactures leading-edge logic chips in the United States ²¹.

The stake is passive, with no board seat ²¹. The government agreed to vote with Intel's board on matters that need shareholder approval, with limited exceptions ²¹. The deal also gave the government a five-year warrant, a right to buy a further 5 percent of Intel at $20 a share ²¹. The government can use that right only if Intel's ownership of its foundry business falls below 51 percent ²¹.

In 2026 Intel began high-volume manufacturing of some of its Panther Lake processors using ASML's High-NA extreme ultraviolet scanners ⁷. It also put its 18A-P process into risk production, the trial runs a process goes through before it is signed off ⁷.

In 2022 Samsung broke ground in Taylor, Texas, on a plant with an initial minimum investment of $17 billion, split into $6 billion for buildings and $11 billion for equipment ²². In December 2024 the Commerce Department awarded Samsung up to $4.745 billion of CHIPS Act funding, to support more than $37 billion of planned investment in Central Texas ²³. That plan covers two new leading-edge logic fabs and a research fab in Taylor, and an expansion of Samsung's existing plant in Austin ²³.

The chokepoint

In 2022 South Korea and Taiwan held almost all of the world's logic capacity below 10 nm ²⁴. The United States had almost no capacity below 10 nm that year ²⁴. In May 2024 SIA and BCG projected that the US share of that capacity would reach 28 percent by 2032 ²⁴. They also projected that new fab investment worldwide would reach around $2.3 trillion from 2024 to 2032 ²⁴.

Across all nodes, old and new, SEMI forecast in June 2024 that China would have installed capacity of 10.1 million wafers a month in 2025, the most of any region ¹⁵. It forecast 5.8 million for Taiwan, out of a world total of 33.7 million, all counted in the 8-inch size ¹⁵. In the third-quarter 2026 update of its World Fab Forecast, SEMI projected that China would keep the largest installed capacity in 2026 and 2027 ²⁵. Little of China's capacity is advanced ²⁴.

Chip production in Taiwan faces three risks:

• Seismic. Taiwan sits on an active plate boundary, and after an earthquake in January 2025 TSMC had to scrap some wafers in process ²⁶.
• Power. A gigafab is a large industrial load on a small island grid.
• Political. Taiwan held 69 percent of the world's logic capacity below 10 nm in 2022 ²⁴. In December 2025 SemiAnalysis put Taiwan's share of the world's advanced-node capacity at over 90 percent, though it did not say which node sizes count as advanced ²⁷. So a blockade or conflict would cut most of that output off from the world market at once. See Geopolitics.

Building capacity outside Taiwan is slow, and TSMC has yet to build a gigafab anywhere else ². SemiAnalysis wrote in December 2025 that a foundry needs highly skilled engineers to get the most working chips from each wafer ²⁷. It judged that finding enough workers remained a major challenge for TSMC in Arizona ²⁷.

An AI accelerator moves numbers from memory to its arithmetic units and back. The cost of arithmetic has fallen faster than the cost of moving numbers. The US export control office wrote in December 2024 that a processor cannot reach its full capabilities unless its memory capacity and bandwidth rise with its speed ¹.

How it works

Each layer in the cube is a DRAM chip, the ordinary kind of computer memory. Each layer is ground thin and bonded to the one below through tiny metal bumps called microbumps. The whole stack sits on a base die, a chip that manages it. The copper-filled holes are called through-silicon vias, or TSVs. They let a signal reach any layer without a wire running around the outside.

An HBM3E cube has a 1,024-bit interface, meaning it exchanges data with the processor over 1,024 wires at once ². That is sixteen times wider than a standard DDR5 memory module, the memory stick in a PC ². HBM4 doubles that to 2,048 wires ³. Ordinary memory cannot be made that wide, because the pins would not fit on a circuit board. The stack can, since its wires run down through the TSVs and across a silicon interposer to the processor beside it, with no board in the way ².

Inside a memory stack

1. 01Base chip
2. 02Thin
3. 03Stack
4. 04Height
5. 05Width

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A memory stack sits beside the GPU on a shared silicon base. It starts with a base chip, which controls the memory chips above it.

1. Base chip. A memory stack sits beside the GPU on a shared silicon base. It starts with a base chip, which controls the memory chips above it.
2. Thin. Each memory chip is ground to about 30 micrometers, thinner than a human hair.
3. Stack. Twelve chips are joined by dots of solder, and copper-filled holes run straight down through all of them.
4. Height. The stack has to fit under the cooling plate. Twelve chips reach 0.72 mm, the old limit. HBM4 raised the limit to 775 micrometers and fits up to sixteen chips.
5. Width. An HBM3E stack talks to the processor over 1,024 wires at once, sixteen times as many as a PC memory module. HBM4 doubles that to 2,048.

Simplified cross-section. Heights follow the published limits and are drawn to one vertical scale. Widths are not to scale.

A chip needs the width most when it answers a prompt. Training reuses each stored number across a huge multiplication, so a chip can fetch little and compute a lot. But to generate one word of an answer, the chip reads the whole model from memory, plus the whole record of the conversation so far. Then it does a little arithmetic and waits for the next read. That record grows with the length of the conversation and the number of users served at once. So memory size and speed usually set how many people one chip can serve.

Variants and trade-offs

HBM3E

Micron's HBM3E comes in two sizes, 24 GB with eight chips stacked and 36 GB with twelve ⁴. SK hynix's January 2026 market outlook says major research and brokerage analysts expect HBM3E to be about two thirds of all HBM shipments in 2026 ⁵.

HBM4

The standards body JEDEC published JESD270-4 in April 2025, setting the 2,048-bit interface and 2 TB/s per stack at 8 Gb/s per pin ³. SK hynix says it was first to complete HBM4 development, in September 2025, at over 10 Gb/s per pin ⁶. Samsung says it began mass production and shipped the first commercial HBM4 in February 2026, at 11.7 Gb/s per pin, with a 4 nm logic base die ⁷. Micron's parts run above 11 Gb/s for more than 2.8 TB/s per stack ⁸.

Through HBM3E, SK hynix made its own base dies, the chips at the bottom of each stack ⁹. For HBM4 it chose TSMC's advanced logic process, so the base die can hold more functions ⁹. As a result, TSMC, which does not make HBM, makes the base die for SK hynix's HBM4.

How a stack is built

• Drill and thin. Etch vertical holes, the through-silicon vias, into a memory wafer, fill them with copper, then grind the wafer from behind until the copper comes through.
• Stack and join. Thermocompression bonding joins the chips through metal bumps under heat and pressure, and it comes in several forms ¹¹. SK hynix uses Advanced MR-MUF, which stacks the chips, injects a liquid protective material between them and hardens it ⁶. SK hynix says the process controls warping and dissipates heat well ⁶. Samsung said in February 2024 that its twelve-high HBM3E uses TC-NCF, thermocompression with a thin non-conductive film between the chips ¹². Samsung expected TC-NCF to help limit warping as chips get thinner ¹².
• Stay under the height limit. HBM4 raised the package specification height of a finished cube from 720 micrometers to 775, still under a millimeter ¹¹.

Hybrid bonding is the next step, but it is not ready. It would press copper pad straight onto copper pad, with no solder and no filler, and cut the spacing between connections from about 20 micrometers to under 1 ¹¹. A tech note on SK hynix's newsroom says full-scale adoption in HBM is most likely at HBM4E or HBM5, where stacks are projected to pass twenty layers ¹¹. Heat builds up in the stack, and removing it becomes a major challenge at 16 to 20 layers ¹¹.

Who makes it

Three firms took more than 90 percent of the revenue from ordinary computer memory, or DRAM, in the first quarter of 2026 ¹³. HBM comes from the same three, SK hynix, Samsung and Micron ¹³. No other company has both leading-edge DRAM and a stacking line of its own.

SK hynix was the first company to mass-produce several generations of HBM, including HBM3 and HBM3E ¹³. UBS, as quoted in SK hynix's January 2026 market outlook, expected SK hynix to take about 70 percent of the HBM4 market for Nvidia's Rubin platform in 2026 ⁵.

SK hynix broke ground in August 2026 on an advanced packaging plant in West Lafayette, Indiana, an investment of over $4 billion ¹⁴. Micron is modernizing its DRAM and HBM production capacity in Taiwan ¹⁵. It has also broken ground on an HBM advanced packaging plant in Singapore to expand its packaging capacity from 2027 ¹⁵.

Of 2025 HBM revenue, SK hynix took 63.2 percent, Samsung 19.3 and Micron 17.4 ¹³. The split is public because SK hynix registered shares in the United States ¹³. Its US prospectus credits the research firm IDC. Market shares move fast. In 2024 the same three stood at 56.4, 37.8 and 5.8 percent ¹³. In the first quarter of 2026 they stood at 56.4, 20.5 and 23.1 percent ¹³.

Bank of America, in an estimate SK hynix quoted in January 2026, put the 2026 HBM market at $54.6 billion, up 58 percent on 2025 ⁵. SK hynix says HBM needs more wafers than traditional DRAM, the kind used in PCs and phones ¹³. It also says the industry's shift of production capacity to HBM has left traditional DRAM undersupplied ¹³. The shortage, it says, helped drive a significant price recovery for that DRAM from the third quarter of 2025 ¹³.

The chokepoint

Every leading accelerator made outside China depends on Korean or American HBM. Nvidia's GB300 NVL72 rack carries 20 TB of HBM3E at up to 576 TB/s ¹⁶. Each Nvidia Rubin GPU carries up to 288 GB of HBM4 at up to 22 TB/s ¹⁷. AMD's MI355X carries 288 GB of HBM3E at 8 TB/s ¹⁸.

On 5 December 2024 the Bureau of Industry and Security (BIS), the US export control office, published a rule at 89 FR 96790. It added an export classification, ECCN 3A090.c, for "High bandwidth memory (HBM) having a 'memory bandwidth density' greater than 2 gigabytes per second per square millimeter". Its technical note defines that density as the memory bandwidth in gigabytes per second divided by the area of the package or stack in square millimeters. The rule also covers stacks made outside the United States, through a foreign direct product rule, which applies US controls to goods made abroad with American technology ¹. BIS stated in the rule that all HBM stacks then in production exceeded that threshold ¹.

Under 15 CFR 742.6(b)(10)(ii), BIS reviews license applications to send 3A090.c items to Macau or a Country Group D:5 destination such as China ¹⁹. It reviews them with a presumption of approval when neither the buyer nor its ultimate parent is headquartered in one of those places, and with a presumption of denial otherwise ¹⁹.

Two provisions narrow the control. License Exception HBM, at 15 CFR 740.25, applies to exporters headquartered in the United States or a Country Group A:5 ally ²⁰. It lets them ship HBM below 3.3 GB per second per square millimeter without a license ²⁰. The HBM must be bought directly by the designer of the chip it will be packaged into and must go straight to the packaging site ²⁰. The rule also excludes co-packaged chips that combine HBM and logic and whose main function is processing, which other chip controls may cover instead ¹.

The think tank CSIS said in December 2024 that the rules still allowed HBM2 to go to China with end-use and end-user restrictions ²¹. It also said Nvidia's H20, whose HBM3 is packaged with the processor, was then still exportable under the accelerator thresholds ²¹.

In December 2024 CSIS called China's strongest DRAM maker, CXMT, one of only two Chinese firms with a credible path to producing advanced HBM ²¹. The Institute for Progress reported in October 2025 that CXMT was planning to produce HBM3 in 2026 ²². It also estimated that China would make virtually no HBM in 2025 ²². Huawei said in September 2025 that its Ascend 950 chips would use two HBM designs of its own, HiBL 1.0 and HiZQ 2.0 ²³. It said the 950DT, due in the fourth quarter of 2026, would carry 144 GB of HiZQ 2.0 at 4 TB/s ²³. The announcement did not say who would manufacture the memory ²³. SK hynix says HBM needs advanced production processes, such as TSV packaging, and must pass the rigorous testing and approval processes its customers set ¹³.

A lithography scanner prints a rectangle 26 mm by 33 mm, or 858 mm2, in one exposure ¹. That area is called the reticle field. Every leading AI accelerator is bigger than that. Packaging is the stage that lets an accelerator be larger than one reticle field, and the packaging method limits how much larger it can be.

How it works

A second reason for the interposer is high bandwidth memory (HBM). An HBM4 stack connects through 2,048 data signals, packed too tightly for a standard resin substrate, so the memory sits beside the logic on the interposer ². Even Nvidia's H100, whose single logic die is 814 mm2 and fits inside one reticle field, carries five HBM stacks ³. Epoch AI counts TSMC's CoWoS packaging among the three inputs the H100 needs, along with its logic die and its HBM ⁴.

The parts of an AI accelerator

1. 01Package base
2. 02Silicon base
3. 03Logic chips
4. 04Memory
5. 05One package

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An AI chip is built from several parts. First comes the package base, a layered board that connects everything to the circuit board below.

1. Package base. An AI chip is built from several parts. First comes the package base, a layered board that connects everything to the circuit board below.
2. Silicon base. On it sits a thin slab of silicon, called an interposer. Its fine wiring joins everything placed on top.
3. Logic chips. Two logic chips go in the middle. They do the calculating, and each is as large as a chipmaking machine can print.
4. Memory. Eight stacks of memory go beside them, a few millimeters away. They hold the AI model’s weights and the record of each conversation so far.
5. One package. Together they make one AI accelerator. Nearly every one is put together by TSMC, in Taiwan.

Simplified view of a two-die, eight-stack accelerator. Footprints follow the sizes given in this chapter and chapter 10. Heights are exaggerated so each layer shows.

CoWoS stands for chip on wafer on substrate, the order in which the parts are joined. For CoWoS-S, TSMC makes a thin silicon wafer that carries wiring and vertical copper vias but no transistors. Vias are metal-filled holes that join one layer of wiring to the next. TSMC bonds the logic dies and memory stacks face down onto that wafer with microbumps. These are dots of solder 30 to 40 microns apart, about a third of a hair's width, and each dot is one electrical joint. Then TSMC cuts the interposer out of the wafer and attaches it to the resin substrate, which later goes onto a circuit board.

Each of those packaging steps is ordinary on its own. But one cracked joint scraps a package holding eight tested HBM stacks and two large, expensive logic dies.

Variants and trade-offs

2.5D: silicon, RDL and bridges

In 2.5D packaging the chips sit side by side and connect through an interposer or silicon bridges beneath them. TSMC has run CoWoS in volume since 2012 ⁵. CoWoS-S has the finest wiring, but its interposer is one unbroken piece of silicon whose yield (the share of interposers that work) falls as the area grows. CoWoS-L replaces that piece of silicon with redistribution layers (RDL) of fine copper wiring and embeds small silicon bridges where the wiring is densest ⁶. Intel's EMIB embeds similar silicon bridges in the resin substrate, and SemiAnalysis reported in March 2026 that Amazon's Trainium and Google's TPU were adopting it to different degrees ⁷.

Blackwell was the first high-volume design on CoWoS-L, and packaging problems at TSMC and in Nvidia's design limited its supply ⁸. The bridges that carry the 10 TB/s link between the two logic dies must be placed very precisely ⁸. The dies, bridges, interposer and substrate also expand at different rates, and that mismatch caused warpage ⁸.

3D: SoIC and Foveros

TSMC's SoIC and Intel's Foveros bond dies face to face, copper pad to copper pad, with no solder. That lets the connections sit far closer together than microbumps allow. TSMC put 3 nm SoIC into volume production in 2025 ⁶. An A14-on-A14 version, stacking dies made on TSMC's 1.4 nm process, is due in 2029 ⁹. It will carry 1.8 times the die-to-die connection density of the 2 nm version ⁹.

In a stack the bottom die overheats and the top die is hard to power. Because of the heat, 3D designs often put cache memory underneath and compute circuits on top.

SoIC bonding also brings optics into the package. TSMC's COUPE uses SoIC to join a silicon photonics chip, which sends data as light, to its electrical control chip ⁶. TSMC said in April 2026 that COUPE on substrate would begin production in 2026 ⁹. It also said that putting COUPE inside the package gives twice the power efficiency of a pluggable version on the circuit board ⁹.

Two ways off the silicon interposer

Panel-level packaging replaces the round wafer with a rectangular panel, which wastes far less area. See Test and assembly. JEDEC, the semiconductor standards body, published a standard called SPHBM4 on 13 July 2026. It puts HBM4 memory on a base chip carrying 512 data signals instead of 2,048 ². With fewer signals, the connections can be spaced widely enough to mount the stack on a standard resin substrate instead of the silicon interposer ².

Capacity

TSMC does not publish its CoWoS capacity ⁴. Industry estimates from SemiWiki and TrendForce, compiled by Epoch AI, put it at about 65,000 to 75,000 wafers a month at the end of 2025, up from 35,000 to 40,000 a year earlier ⁴.

At its 2024 symposium TSMC said CoWoS capacity would grow at a 60 percent compound annual rate over the next few years ¹⁰. But when asked about that rate on the July 2024 earnings call, TSMC's chief executive, C.C. Wei, gave no figure ¹⁰. He said only that he would keep adding capacity wherever he could, and that he could not yet balance supply and demand ¹⁰.

In October 2025 Wei would still say only that TSMC was working to increase capacity in 2026 and would probably give the real number in 2026 ¹¹. He said front-end capacity (making the chips) and back-end capacity (packaging them) were both, in his words, very tight ¹¹.

Epoch AI compared each chip designer's use of components with world supply ⁴. It puts Nvidia at 60.3 percent of all CoWoS capacity in 2025, with a 90 percent confidence interval of 56.5 to 64.3 ⁴. Google took 13.5 percent, AMD 8.4 and Amazon 7.4 ⁴. Together those four used around 90 percent of global CoWoS capacity and HBM supply, with HBM measured by value, but only 12 percent of advanced logic die production ⁴.

In March 2026 the research firm SemiAnalysis judged that front-end capacity had become the dominant bottleneck and that CoWoS constraints were easing ⁷. It said TSMC was planning CoWoS capacity around how many wafers N3, its 3 nm process, could produce, because added packaging capacity is of no use without front-end wafers to fill it ⁷.

TSMC gave a different account four months later. On the July 2026 earnings call, Wei said TSMC's packaging capacity was so tight that it limited customers' growth, and that back-end capacity was still in shortage ¹². Asked about Intel's EMIB-T, he said he welcomed the extra flexibility and hoped it would take some of the load off TSMC ¹².

Who makes it

Three kinds of firm package chips. TSMC, which makes chips for others, and Intel, which makes its own, do it in their own back-end fabs. Outsourced assembly and test firms do the rest. Intel opened Fab 9 in Rio Rancho, New Mexico, in January 2024 to make its Foveros 3D packages in volume ¹³. It called the plant the only US factory producing the most advanced packaging at scale ¹³.

ASE Technology Holding, the leading provider of assembly and test services, had revenue of NT$645.4 billion in 2025, about 40 percent of it from electronics manufacturing services ¹⁴. Its assembly, test and materials business brought in NT$389.2 billion, up from NT$325.9 billion in 2024 ¹⁴. Amkor, the largest US-headquartered assembly and test firm, had net sales of $6.71 billion in 2025 ¹⁵.

The packaging tools are a narrower chokepoint than the assembly firms.

• Thermocompression bonding. Pressing dies together under heat and force. ASMPT's advanced packaging revenue reached $532.1 million in 2025, with thermocompression bonder revenue up about 146 percent ¹⁶. ASMPT targets 35 to 40 percent of a market it puts at $1.6 billion in 2028 ¹⁶.
• Hybrid bonding. Copper pads bond directly, with no solder. Applied Materials co-developed its Kinex hybrid bonding system with Besi, which Applied calls the industry leader in hybrid bonding ¹⁷.
• Grinding and dicing. Disco held 87 percent of the $1.9 billion world market for dicing tools in 2025, by CSET's count from TechInsights data ¹⁸. The category covers the grinders that thin wafers and the saws that cut them into chips ¹⁸. See Test and assembly.

TSMC's Arizona commitment reached $265 billion in July 2026 and covers two advanced packaging plants alongside 10 fabs ¹⁹. Amkor started building a $7 billion campus in Peoria in October 2025 and expects production from early 2028 ²⁰. The Commerce Department awarded Amkor up to $407 million in CHIPS Act funding for the site in December 2024 ²¹. In October 2025 Wei said a large outsourced packaging partner, already breaking ground in Arizona, was on an earlier schedule than TSMC's own two packaging fabs there ¹¹.

The chokepoint

Four of the top ten outsourced assembly and test firms by 2024 revenue are headquartered in China ²². JCET, a leading Chinese assembly and test firm, had record revenue of RMB 38.87 billion in 2025, up 8.1 percent ²³. JCET says its XDFOI platform has entered high-volume manufacturing with redistribution-layer interposer, silicon interposer and silicon bridge options ²⁴.

Between 2019 and 2024, Chinese firms gained 5 percentage points of share in test tools and 4 points in fabrication tools built for advanced packaging ²². But they lost share in bonding and other conventional assembly and packaging tools, the category where CSET counts hybrid and thermocompression bonders ²². Within the advanced packaging fabrication tools, Chinese firms gained 10 points in etch and clean tools and 3 points in deposition tools, and lost 2 points each in lithography and polishing (CMP) tools ²². In 2024 Chinese firms had 7 percent of the market for advanced packaging fabrication tools, against 65 percent for US firms and 15 percent for Japanese firms ²².

Each generation on TSMC's roadmap needs a larger interposer.

• 2028. A 14-reticle interposer of roughly 12,000 mm2, about the area of a compact disc, carrying about ten large compute dies and 20 HBM stacks ⁹.
• 2029. More than 14 reticles, plus a 40-reticle System-on-Wafer ⁹.

The silicon interposer wires chips together inside a package. Beyond the interposer, the wiring runs through a build-up substrate made of epoxy and glass, then a printed circuit board of thirty layers, then a server rack.

How it works

How a substrate fans out

1. 01The package
2. 02Tight to wide
3. 03Layer by layer
4. 04Connected

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An AI chip is more than the chip itself. It sits in a package: the chips on a silicon base, and under them the substrate, which connects everything to the circuit board.

1. The package. An AI chip is more than the chip itself. It sits in a package: the chips on a silicon base, and under them the substrate, which connects everything to the circuit board.
2. Tight to wide. The connections on top are packed tight. The circuit board below is wired in millimeters. The substrate has to join the two.
3. Layer by layer. The substrate does it in layers, built outward from a stiff core. Each layer carries the copper a little further out.
4. Connected. Stacked together, the layers fan the tight grid out to the board’s wide one. An AI chip needs about 18 layers, against six for a PC, and every layer is another chance for a flaw, which is what makes these substrates hard to build.

Simplified. Eight layers are drawn, and every thickness is exaggerated.

The substrate maker drills the core and plates it with copper before the build-up starts. In each cycle the maker then presses on a film of epoxy, burns holes through it with a laser to connect the layers, and adds copper wiring on top ¹. Each film is about 10 micrometers thick, and a human hair is about 80 micrometers across ².

Ajinomoto counts 22 layers of its film in a 2026 AI package substrate about 100 mm square, against 18 on a high-performance computing substrate about 70 mm square around 2023 ¹. PC substrates had six layers of the film when PCs first adopted it in 1999 ¹. Silicon and epoxy swell at different rates when heated, so the larger the package, the more it warps. Nitto Boseki says its low-expansion T-glass cloth is highly rated as an effective fix for that warping, and that its use in substrates has increased significantly ³.

Variants and trade-offs

BT substrates

Substrates built on bismaleimide-triazine laminate, or BT, are the other main family. Mitsubishi Gas Chemical, which makes BT materials, says they go mostly into thin packages for smartphone processors, radio modules and memory ⁴. The company says BT also goes into flip-chip substrates for computer CPUs and GPUs ⁴. In these the chip is mounted face down, and BT laminate forms the core between layers of build-up film ⁴. In an October 2024 investor presentation, the company estimated that its BT resins held about 40 percent of the substrate materials market ⁴.

ABF build-up substrates

Ajinomoto Build-up Film, or ABF, is the insulating film between the layers of package substrates for logic chips, used in PCs, network equipment, servers and AI equipment ¹. Ajinomoto first developed it in 1999 and says major chipmakers have used it as the de facto standard ever since ⁵. On Ajinomoto's own site, its electronic materials division said practically all high-performance computers and servers rely on the film ². In June 2026 Ajinomoto told investors that the film has held a share of over 95 percent since its launch ¹.

Glass core substrates

A glass core expands less with heat than a resin core and stays flatter, so chipmakers and substrate makers are both trying it ⁶.

• Absolics, a subsidiary of Korea's SKC, has a final Commerce Department award of up to $75 million for a 120,000-square-foot glass substrate plant in Covington, Georgia ⁷. As of October 2026, the award's project page at NIST, a Commerce Department agency, expected first deliveries to customers in 2025 and production capacity to come online in 2027 ⁷.
• Intel announced glass substrates in September 2023 for the latter part of this decade ⁸.
• Samsung Electro-Mechanics signed a joint venture agreement with Sumitomo Chemical's subsidiary Dongwoo Fine-Chem in July 2026 to make glass core substrates ⁹. The partners plan to have a supply system in place by the second half of fiscal 2027 ⁹.

The materials underneath

Ajinomoto's Healthcare and Others segment, which includes electronic materials such as the film, lifted business profit 45.1 percent to JPY 66.2 billion in the year to March 2026 ¹⁰. Ajinomoto attributes the rise mainly to higher electronic materials revenue and higher profit in Bio-Pharma Services & Ingredients ¹⁰. It has set an investment budget of JPY 25 billion between 2023 and 2030 to expand film production ¹. It says there are no concerns about its current supply chain overall ¹. In May 2026 it announced the acquisition of land in Gifu Prefecture for a third production site, scheduled to start operating in 2032 to meet demand after 2030 ¹.

The glass cloth in the core also has a dominant supplier. Nitto Boseki's T-glass is stiff and expands little when heated, and the company calls it essential for making high-density package substrates ³. Laminate makers such as Mitsubishi Gas Chemical coat the glass cloth with resin and press it with copper foil into the core laminate that substrate makers build on ⁴.

Nitto Boseki claims an overwhelming advantage in quality and capacity for low-expansion glass ³. It planned about JPY 80 billion of capital spending for fiscal 2024 to 2027, and says market demand seems to have risen about two to three times since that plan was set ³. In August 2025 it decided to expand glass fiber cloth production at its Fukushima Enterprise Center, with production scheduled to begin in the fourth quarter of its fiscal 2026 ³. Apple and Qualcomm are among the customers worried about Japanese glass cloth supply ¹¹.

Nitto Boseki says Chinese and Taiwanese companies are aggressively catching up with it in the special glass sector ³. Nikkei reports that Chinese chip materials makers are competing with Japanese rivals for a market it sizes at $73 billion ¹².

Who makes it

A few Asian companies build substrates for other firms. The White House's 2021 hundred-day supply chain review listed build-up substrate among the materials that commenters called vulnerable ¹³. It named key substrate makers including Ibiden, Nanya, Shinko, Samsung, Unimicron, Shennan Circuits, Zhuhai Yueya and AKM, none of them American ¹³.

A May 2024 report by the Semiconductor Industry Association and Boston Consulting Group counted the major package substrate vendors by headquarters ¹⁴. It found two in Japan, two in Taiwan, one in mainland China and none in the United States ¹⁴. TTM Technologies, an American circuit board maker, says it also offers package substrates ¹⁵.

• Ibiden will invest about JPY 500 billion in high-performance package substrates from fiscal 2026 to fiscal 2028, starting with about JPY 220 billion, mainly at its Gama plant in Gifu Prefecture ¹⁶. It planned mass production from fiscal 2027 ¹⁶. In May 2026 management said Ibiden typically takes close to 100 percent of a new generation of interposer-type substrates at launch ¹⁷. It added that this share may decline by 20 to 30 percent after about three to six months ¹⁷. On silicon-bridge substrates, it said wiring the underside is hard enough that Ibiden expects to keep its technical lead at least through fiscal 2030 ¹⁷.
• Unimicron reported NT$42.9 billion of sales in the second quarter of 2026, 52 percent of it build-up substrates and 61 percent of it AI data center work ¹⁸.
• Samsung Electro-Mechanics grew package solution sales 37 percent year on year to KRW 771.6 billion in the second quarter of 2026, on substrates for AI accelerators, server processors and cars ¹⁹.
• AT&S, an Austrian firm, calls itself a globally leading maker of high-end package substrates, which it makes in China, Malaysia and, since its 2025/26 financial year, Austria ²⁰.

In February 2025 a company owned mainly by funds of JIC Capital, a subsidiary of Japan Investment Corporation, launched a tender offer to take Shinko, a Japanese substrate maker, private ²¹. The offer covered the shares Fujitsu did not own, and Fujitsu agreed to sell its 50.02 percent stake back to Shinko ²¹. The tender offer succeeded in March 2025 ²².

In September 2026 Shinko agreed to buy a plant in Mobara, Chiba Prefecture, from Japan Display, a display maker ²³. Shinko said it would make the site a new core plant for advanced chip packages and would also expand capacity at its plants in Nagano ²³. Production at the Mobara plant is scheduled to start in fiscal 2028 ²³.

The boards under the GPU

TTM Technologies says it regularly builds printed circuit boards of more than 30 layers and can go past 70 ¹⁵. Those layers carry power to the GPUs and route fast signals between them, so how much signal the laminate absorbs is a main design constraint. Nitto Boseki also makes NE-glass, a low-dielectric glass cloth that absorbs less signal, used in switches and routers in data centers ³.

Data center computing was 24 percent of TTM's $2.91 billion of fiscal 2025 revenue, against 14 percent two years earlier ¹⁵. TTM says its circuit board competitors are mostly based in China and Taiwan ¹⁵. In its annual report for 2025, TTM said it was building a plant in Syracuse, New York, to make ultra-high-density circuit boards for national security needs ¹⁵. It expected volume production there in the second half of 2026 ¹⁵. Thailand aims to be the biggest circuit board hub outside China as board makers diversify production ²⁴.

The chokepoint

The few firms that build substrates can add capacity by spending money, and they are spending it. The materials inside the substrate are harder to replace. Mitsubishi Gas Chemical, a laminate maker, says chipmakers and electronic device makers further down the chain approve the materials it sells to substrate makers ⁴. Ajinomoto dominates the film, and Nitto Boseki dominates the low-expansion glass cloth in the core. Both are adding capacity on plans that run for years.

Packages are also getting bigger. TSMC told investors in July 2026 that its CoWoS packaging roadmap goes beyond 14 times the area a lithography machine can print in one shot ²⁵. A bigger package warps more and needs more layers, so it has more holes that can break the circuit. That lowers yield, the share of substrates that come out working, and each substrate is already expensive before a chip is mounted on it.