How AI chips
are made

Design is the only stage in this chain without a factory, and one the US government has already restricted by letter. In late May 2025 the US government required a license to sell chip design software to anyone in China, and Cadence cut off its Chinese customers until the rule was lifted on 2 July ¹.

How it works

How a chip is designed

1. 01A blueprint
2. 02One tick
3. 03Too far
4. 04Placed closer
5. 05Checked

Paused

Making a chip starts with design, which turns an idea into a complete blueprint. The blueprint fixes where each of the chip’s billions of switches sits and how each one is wired to the others.

1. A blueprint. Making a chip starts with design, which turns an idea into a complete blueprint. The blueprint fixes where each of the chip’s billions of switches sits and how each one is wired to the others.
2. One tick. The chip works in ticks, each less than a billionth of a second. On every tick a signal leaves a register, a small store that holds one number, and it has to cross its wire to the next register before the next tick.
3. Too far. If the next register sits far away, the wire is long. The signal is still on its way when the next tick comes, so it arrives too late.
4. Placed closer. Design software from three companies, Synopsys, Cadence and Siemens, places the parts and wires them together. Here it moves the register closer, and the signal arrives in time.
5. Checked. The software checks that every signal on the chip arrives in time, and a chip factory accepts only designs that pass. The factory then prints the blueprint onto silicon through stencils, and changing it after that costs new stencils and several months.

Simplified. Not to scale. The floorplan follows a GPU die; one tick, less than a billionth of a second, is slowed to about two seconds.

Design runs in five stages, each one's output the next one's input, all of it in software.

• Architecture. Engineers fix the shape of the chip: how wide the block that multiplies numbers is, how much fast on-chip memory sits beside it, how many high-bandwidth memory stacks line the edges. The output is a plan.
• RTL. Engineers write the plan as register-transfer-level code, RTL, in the hardware language SystemVerilog. A register is a small store on the chip that holds one number, and the clock is the tick that moves every register forward together. The code says what every register holds on every tick, and the output is a text description of the whole chip.
• Verification. A large team checks that the code does what the plan says. They run it in simulation, prove parts of it correct with mathematics, and load it into emulators, cabinets of reprogrammable chips that behave like the design, so the chip's own software can boot before any silicon exists.
• Physical design. Software swaps each piece of the code for a logic cell, a small ready-made circuit the foundry has already proved it can make, then places the cells on the chip, wires them together and proves that every signal arrives in time.
• Tape-out. The handover. Software turns the placed layout into pattern files for the mask shop. First it pre-distorts each shape so that it prints as drawn, which is optical proximity correction; then it cuts the layout into the files a mask writer reads, which is mask data preparation.

All that checking exists because each revision after tape-out needs at least some new masks ². In 2022 SemiAnalysis put a full set at more than $1 million at 28 nm and more than $10 million at 7 nm, and expected 3 nm sets to push into the $40 million range ². Its May 2026 primer still puts a leading-edge mask set at $40 million, and a single respin, a revision after tape-out, at leading-edge nodes at $50 million to $100 million ³. In 2022 SemiAnalysis also reported that startups had taken chips on TSMC 7 nm, then a leading-edge process, from design to tape-out for $50 million to $75 million, everything included ². In September 2026 CSIS put a different measure, the cost of developing a leading-edge 2 nm chip, at about $725 million, against $48 million to develop a 28 nm design in the late 2000s ⁴. The nanometer labels name generations of the process, each finer than the last, and no longer measure anything.

Variants and trade-offs

Merchant GPU versus custom ASIC

Nvidia designs Blackwell once and sells it to everyone, so the buyer gets mature software and a resale market. A custom accelerator, an ASIC built for one company's own workload, is narrower and tuned to that one workload. Google's seventh-generation tensor processing unit, Ironwood, carries 192 GB of memory per chip, six times its predecessor's, and delivers twice the performance per watt ⁵.

The EDA flow

Three complete flows exist, and a change of synthesis tool means re-running place-and-route, signoff and physical verification ³. Foundries also specify which signoff tools their customers must use for tape-out ³. Synopsys alone holds more than 90 percent of static timing analysis, the check that proves a chip will run at its rated speed ³, so inside some steps of the flow one vendor holds most of the market.

Buy the IP or build it

Design houses license the processor cores, the interface controllers and the blocks that drive high-bandwidth memory. Arm licenses processor designs, and in fiscal 2026 it reported $4.92 billion of revenue, $2.61 billion of it royalties, and said it held about 50 percent of processor compute at the top cloud firms ⁶. In 2026 Arm also launched the Arm AGI CPU, its first production silicon product, and by May 2026 servers built on it could be ordered from ASRock, Lenovo, Quanta and Supermicro ⁶. The memory interface is a demanding block, because it has to hold its timing across thousands of microscopic solder bumps into a stacked memory die. RISC-V, the open instruction set that needs no license, handles the small control tasks on the chip, and Nvidia now uses it in every GPU ⁷.

Chiplets

The reticle limit, the largest area a scanner can print in one exposure, limits how large a single die can grow ⁸. Many large accelerators are built from chiplets, several smaller dies wired together, and UCIe is an open industry standard for the links between them inside a package ⁹. Version 3.0 of UCIe adds 48 and 64 GT/s data rates ⁹. Broadcom's 3.5D XDSiP platform packs more than 6,000 mm2 of silicon and 12 high-bandwidth memory stacks into one package ⁸.

Who makes it

Design software and licensed blocks were an $18 billion market in 2025, and Synopsys, Cadence and Siemens EDA took more than 85 percent of it, counting Ansys as part of Synopsys, with no other vendor above 5 percent in any core category ³.

Synopsys is the largest. Its own results put revenue at $7.054 billion for the fiscal year to 31 October 2025, with Ansys, bought that July, contributing $756.6 million ¹⁰. Cadence, whose year ends in December, took $5.297 billion in calendar 2025 ¹¹. The two fiscal years do not line up, so any total for this market depends on which twelve months are counted and on how much of Ansys it includes. SemiAnalysis counts Synopsys at $8 billion for calendar 2025 with Ansys included, and it puts 31 percent of Ansys's business in semiconductors and high technology, 22 percent in aerospace and 18 percent in automotive ³.

Some chip firms also build custom accelerators to a customer's design and sell the finished chips. Broadcom booked $16.7 billion of AI semiconductor revenue in the third quarter of fiscal 2026, up 221 percent year over year, a figure that covers both its custom AI accelerators and its AI networking chips ¹².

In October 2025 OpenAI and Broadcom said they would deploy 10 gigawatts of OpenAI-designed accelerators, with Broadcom turning the design into silicon and supplying the Ethernet networking around it ¹³. In April 2026 Broadcom extended its Meta partnership to multiple gigawatts of MTIA, Meta's in-house chip, and the first 2 nm AI accelerator ¹⁴.

Below Broadcom and Marvell sit the Taiwanese design-service houses that carry a customer's circuit list all the way to a finished mask set on TSMC's newest nodes; Alchip reported $992 million of revenue in 2025 ¹⁵. The engineers are spread across more countries than the firms, and India alone holds nearly 20 percent of the world's chip designers ¹⁶.

The chokepoint

A narrower control came first. Since 14 October 2022, design software specially made for chips with gate-all-around transistors, a design the rule calls key to processes at 3 nm and below, has needed a US export license for national-security reasons ¹⁷. That license requirement covers exports to China ¹⁸. The control carried out a December 2021 decision of the Wassenaar Arrangement, the multilateral export-control group ¹⁷.

In late May 2025 the US Bureau of Industry and Security, the agency that writes export licenses, told the design-software vendors that sales to China now needed a license ¹. Cadence got its letter on 23 May: exporting design software classified 3D991 and 3E991 to any party in China, or to a Chinese military end user anywhere, now needed a license ¹. Synopsys got its letter on 29 May and a rescinding letter on 2 July ¹⁹.

Washington imposed the 2025 requirement alone, and at once. Synopsys's China revenue fell from 16 percent of its total in fiscal 2024 to 12 percent in fiscal 2025 ³. SemiAnalysis links the decline to tighter export restrictions and to local design-software companies winning share at mature nodes ³. SemiAnalysis also quoted Synopsys's management saying that the companies it cannot sell to look for alternatives, typically local design-software and licensed-block companies ³.

In October 2025 CSIS found that only a few companies, Cadence, Synopsys and Siemens, make design software that supports the entire chip design flow of more than 40 steps ²⁰. In a January 2021 report built on 2019 market data, CSET at Georgetown University found that one Chinese firm, Empyrean, could reportedly run a complete design flow only for certain analog and mixed-signal chips, which combine analog and digital circuits ²¹. Outside that niche, Chinese designers then relied on US tools for all chip designs ²¹. The report found that other Chinese tools covered only narrow parts of the design flow or supplemented US tools, and largely did not support processes at 14 nm and below ²¹. In its 2025 annual report, filed in April 2026, Empyrean says it now has complete design flows for analog, memory, radio-frequency and flat-panel display circuits, and that its digital tools cover 80 percent of the main tools for digital design ²². The same report lists foundry certifications for its circuit simulator at 8, 5 and 4 nm and for its physical verification tool, the final layout check, at 28 nm ²². CSIS found that as of 2025 Chinese design tools were still far from replacing the full range of advanced capabilities US firms offer, especially for 5 nm and 3 nm chip design ²⁰.

China can design an accelerator. It cannot finish one at the leading edge without foreign tools, or build what it designs without foreign equipment. In June 2024 CSET found that SMIC's limited 7 nm capacity forced Huawei to choose between making its most advanced phone chips and its AI chips ²³.

On Epoch AI's estimates, Huawei's flagship chip for 2026, the Ascend 950, delivers about half the computing performance of Nvidia's H100, which began shipping in 2022, and Nvidia's B300 has 6.75 times the 950's theoretical peak performance ²⁴. Epoch's median estimate is that Huawei will make about 1.5 million Ascend chips in 2026, against 5.9 million for Nvidia ²⁴. On those estimates, Huawei's 2026 output would carry less than 4 percent of the computing power Nvidia ships that year ²⁴. Epoch puts Huawei's chips three to four years behind Nvidia's until at least 2030, for three reasons. SMIC, which makes Huawei's chips, cannot pack transistors as densely as TSMC, which makes Nvidia's. Chinese memory makers are only starting to produce high-bandwidth memory. And Huawei's software for programming its chips is far less mature than Nvidia's ²⁴.

Key evaluation criteria

• Flow completeness. How many steps one vendor covers, from the first line of code to final signoff.
• Foundry certification. Whether the foundry has validated that exact tool version against its reference flow and process design kit, the file set describing what the factory can print. Without that, the foundry refuses signoff.
• Verification throughput. Simulation cycles and emulator capacity per day, which set the schedule more than anything else.
• IP availability at node. Whether the licensed blocks, the processor cores, the high-speed serial links, PCIe and the memory interface, have been proven in silicon on that process.
• Design services depth. Whether a partner can carry a customer's circuit list to a finished mask set on the newest node.
• Legal exposure. How much of the flow is US-origin technology, and so subject to export licensing.

The whole world market for silicon wafers came to $11.4 billion of revenue on 12,973 million square inches in 2025 ¹. That is a small fraction of Nvidia's data center revenue, which reached $193.7 billion in the fiscal year to January 25, 2026 ².

How it works

From sand to wafer

1. 01Refine
2. 02Grow
3. 03Slice
4. 04Polish

Paused

Silicon starts as sand and rock. It is refined into rods so pure that, of every hundred billion atoms, fewer than one is anything else.

1. Refine. Silicon starts as sand and rock. It is refined into rods so pure that, of every hundred billion atoms, fewer than one is anything else.
2. Grow. The rods are melted. A seed crystal touches the melt and is drawn slowly up, turning, and the silicon freezes onto it as one long crystal.
3. Slice. A wire saw slices the crystal, called an ingot, into thin discs.
4. Polish. Each disc is ground, etched and polished until it is flat to within a few atoms, right out to the edge.

Simplified. The ingot and the machines are not drawn to scale.

Silicon starts as quartzite, a rock that is silicon bound to oxygen. An arc furnace melts it with carbon, and the carbon takes the oxygen away as gas, leaving rough silicon metal. Refiners turn the metal into a gas, trichlorosilane, and distill it, because the impurities boil at other temperatures and stay behind. The clean gas then flows over silicon filaments heated inside a bell jar. On the hot surface the gas breaks apart, its silicon settles onto the filaments, and over days the filaments thicken into gray rods of polysilicon, the Siemens process. Everything downstream is made from those rods. Polysilicon comes in two ultra-high-purity grades, one for semiconductors and one for solar cells, and chips use the semiconductor grade ⁵.

A grower melts the polysilicon at about 1,420 degrees Celsius, hotter than lava, and pulls a single crystal out of it by the Czochralski method ³. The grower lowers a small seed crystal on the end of a rod to the surface of the melt and draws it back up, slowly turning. Silicon freezes onto the seed in the seed's own atomic pattern, and a cylinder grows beneath it, the ingot. The pull starts with a thin neck so that the flaws formed where the seed first touched the melt end in the neck and never reach the ingot. Boron or phosphorus stirred into the melt, a step called doping, sets how readily the wafer conducts and whether the current in it is carried by negative charges or positive ones.

A wire saw, a web of fine wire running through abrasive, slices the ingot into discs. The maker then laps each disc, grinding both faces flat between rotating plates, chemically etches off the damaged surface, and polishes it to a mirror with colloidal silica, a slurry of silica particles far too small to see. Epitaxial wafers get one more layer of near-perfect silicon grown on top at about 1,200 degrees Celsius ³, still hot enough to glow orange, and almost every step throws material away.

Variants and trade-offs

Polished versus epitaxial

A polished wafer is a doped single crystal polished to a mirror finish ³. An epitaxial wafer is a polished wafer with a thin layer of single-crystal silicon grown on top at about 1,200 degrees Celsius ³. The transistors live in that layer, so its quality sets the lowest leakage the chip can reach and its risk of latch-up, a parasitic short between power and ground. SEMI, the industry association, credits the 2025 rise in shipments to AI-driven demand for advanced epitaxial wafers in logic and polished wafers for high-bandwidth memory ¹.

Silicon on insulator

A buried layer of oxide, which is glass, separates a thin working layer of silicon from the bulk beneath, and Soitec's Smart Cut process makes nearly all of it ⁶. Soitec's SOI product lines include RF-SOI for radio chips and FD-SOI, and its markets run from mobile communications to cloud AI ⁶. SEMI tied the AI-driven growth in logic to advanced epitaxial wafers ¹.

Who makes it

In a January 2021 brief, CSET at Georgetown named Shin-Etsu, SUMCO, GlobalWafers, Siltronic and SK Siltron, headquartered in Japan, Taiwan, Germany and South Korea, as key wafer firms ⁷. It also listed nine Chinese-owned producers, among them Zhonghuan, Simgui, ZingSEMI and Finland's Okmetic, but said they generated little revenue in comparison ⁷. As of 2018, five Chinese firms were making or planning 300 mm wafers ⁷. Eswin's October 2025 listing prospectus counts seven Chinese firms, Eswin included, making 300 mm wafers at scale, with a combined capacity of 2.94 million wafers a month at the end of 2024 ⁸.

The chart shows shares of 2023 sales from a survey by Fuji Keizai, a Japanese research firm, relayed in the December 2025 strategy deck of Japan's Ministry of Economy, Trade and Industry ⁹. The deck prints only Japan's 53 percent, so the other shares are read off its chart, which gives no separate share to Chinese or US companies ⁹. Siltronic's April 2026 investor presentation says the top five wafer makers serve around 75 percent of the market, based on revenue in the first three quarters of 2025 ⁴.

Their 2025 results split between an AI boom and a slump in the older, mature nodes.

• Shin-Etsu. Its parent's electronics materials segment sold ¥1,015.7 billion in the year to March 2026, up 9 percent, as AI-related demand stayed strong and demand in other sectors began to rise, lifting sales of silicon wafers, photoresist and photomask blanks ¹⁰. The segment also sells rare earth magnets and other materials, and the results release does not break out wafer sales, so the figure cannot be compared with the wafer revenue of the other firms here ¹⁰.
• SUMCO. Sold ¥409.7 billion and still lost ¥11.8 billion, as operating profit fell from ¥36.9 billion to ¥1.3 billion while it added leading-edge 300 mm capacity and reorganized production of 200 mm and smaller wafers, where demand stayed weak ¹¹.
• Siltronic. Lost €77.9 million on €1,346.7 million of sales while investing €369.1 million, with its new Singapore fab as the focus ¹².
• GlobalWafers. NT$60.6 billion of revenue, down 3.24 percent in local currency ¹³.

Area shipped rose 5.8 percent in 2025 while revenue fell 1.2 percent ¹. SEMI attributes the softer revenue mostly to traditional chip applications, where demand and pricing had yet to improve ¹.

China made 1.50 million metric tons of polysilicon, the raw material, in 2023, about 93 percent of world output ¹⁴. Solar-grade material was an estimated 98 percent of that output and electronic-grade 2 percent ¹⁴. The Commerce Department found in 2026 that semiconductor-grade polysilicon makes up only 2.4 percent of global production, a split close to China's ¹⁵. The share alone does not show whether Chinese polysilicon goes into chips.

Siltronic put the 2025 market for electronic-grade silicon at $1.4 billion, with five major suppliers, none of them Chinese: Wacker, Hemlock, OCI, Tokuyama and Mitsubishi ⁴.

The leading wafer makers are headquartered in Japan, Taiwan, Germany and South Korea, and Siltronic of Germany describes itself as the only Western-based maker among the top five, based on revenue in the first three quarters of 2025 ⁴. GlobalWafers opened a $3.5 billion plant in Sherman, Texas in May 2025, the first production line of its kind built in the United States in over twenty years, and announced another $4 billion for phases three and four the same day ¹⁶. Washington had awarded it up to $406 million under the CHIPS incentives program for wafer plants in Texas and Missouri ¹⁷.

Presidential Proclamation 11052, signed August 6, 2026, sets a minimum import price of $100 per kilogram for polysilicon ingots and wafers and an extra 15 percent duty on imported ingots and other listed products made from polysilicon, both from December 4, 2026 ¹⁵. A September 2026 Commerce rule meant to stop stockpiling before the duties start lists tariff code 3818.00.0040 among the products it covers ¹⁸. That code covers round, doped, single-crystal silicon wafers ¹⁹. Commerce may approve plans to build US polysilicon, ingot, wafer or cell plants whose construction starts by January 20, 2029, and firms with approved plans can import equipment and some of those products without the new duties ¹⁵.

The chokepoint

China dominates polysilicon, and in 2019 it had almost no share in wafers. As of 2019 Chinese firms held under 5 percent of the wafer market and under 1 percent of 300 mm ⁷. As of 2018, Chinese producers made 12 percent of the wafers for Chinese-headquartered 300 mm fabs, against 18 percent for 100 to 200 mm fabs ⁷. Eswin, mainland China's largest maker of 300 mm wafers, says it ranked sixth in the world with about 7.7 percent of global 300 mm shipments in the first half of 2026 ²⁰. Its October 2025 Shanghai listing prospectus, drawing on SEMI data, estimates that the five largest makers shipped about 79 percent of 300 mm wafers in 2024, Eswin about 6 percent and all other makers about 15 percent ⁸.

Making the smoothest, high-purity 300 mm wafers takes considerable know-how that is hard to write down, and 300 mm carried 99.7 percent of world fab capacity at 45 nm and below in SEMI figures from November 2020 cited by CSET ⁷. Counting wafers of every size, SEMI estimated that 300 mm wafers made up about 78.8 percent of the wafer area shipped worldwide in 2025, according to Eswin's 2025 annual report summary ²¹. Customers have to qualify a new wafer plant before they buy from it, and Siltronic completed key customer qualifications at its new Singapore fab in July 2025 ⁴.

The last increase in wafer size, to 300 mm, happened in 2002 ⁷. Bigger discs make printing a bigger share of the processing cost, and a 2013 University of Texas lecture cited by CSET put photolithography at half the cost of processing a 300 mm wafer against a quarter of a 150 mm one ⁷. Wafers are still produced in diameters of up to 300 mm ¹.

One fatal defect ruins far more silicon on a GPU die that fills a whole printed field than on a small chip, and extreme-ultraviolet printing stays in focus over only a very small range of heights (see Lithography), so flatness has to hold at every point on the disc.

Key evaluation criteria

• Grade. Chips need electronic-grade polysilicon, and none of the five major suppliers of it that Siltronic named for 2025 is Chinese ⁴.
• Defect density in the epitaxial layer. A big AI die loses more good silicon per defect than a small chip does, and SEMI's wafer group says the move to sub-3nm processes is raising requirements for wafer quality and consistency ¹.
• Flatness and nanotopography, the fine ripple across the surface, because extreme-ultraviolet exposure stays in focus over only a very small range of heights, and that has to hold across a 300 mm wafer.
• Diameter, where 300 mm carried 99.7 percent of world fab capacity at 45 nm and below in SEMI figures from November 2020 cited by CSET ⁷. Of all the wafer area shipped worldwide in 2025, 300 mm wafers made up an estimated 78.8 percent ²¹.
• Contract structure, since Siltronic expects continued price pressure in 2026 on sales outside its existing long-term agreements ¹².

A modern fab is a chemical plant with lithography attached. Air Liquide alone supplies more than 200 molecules and roughly 50,000 cylinders a year ¹. A shortage of any one of them can stop a fab.

How it works

The resist has to change only where the light lands, and change fast enough that the scanner, the machine that projects the pattern, can expose each patch of the wafer in milliseconds. Since the 1990s the standard resist has been the chemically amplified resist. At 248 nm and 193 nm, a photon absorbed in the film can free an acid molecule, and nothing more happens until the wafer is baked. In the bake, each acid molecule sets off hundreds of reactions around itself that turn the film soluble, so a little light does a lot of chemistry. The wash then takes away the exposed film and leaves the rest. The light comes at 248 nm from a krypton fluoride laser or 193 nm from an argon fluoride laser shining through a layer of water, which sharpens the image.

That chemistry works less well with extreme ultraviolet (see Lithography). An absorbed extreme ultraviolet photon instead knocks electrons loose, and a cascade of lower-energy secondary electrons makes the chemical changes in the resist ³. A 13.5 nm photon carries about fourteen times the energy of a 193 nm one, so the same dose of light arrives as far fewer photons. With fewer photons, where each one happens to land matters, and that randomness shows up as ragged line edges and missing contact holes, the small wells that join one layer of wiring to the next. Resist makers answered with metal-oxide resists, built on clusters with a tin-oxide core, which absorb more of the extreme ultraviolet light than chemically amplified resists ⁴. In 2021 JSR agreed to buy Inpria, an Oregon maker of these resists ⁵.

Everything else puts material on the wafer, takes it off, or keeps it clean. Bulk gases arrive by the metric ton, specialty gases in grams. Silane carries silicon into the chamber for deposition. A plasma tears nitrogen trifluoride into charged fragments, which scrub the chamber walls clean between wafers. Hydrofluoric acid cleans the wafer itself. Polishing slurries grind each new layer flat before the next goes on. Sputtering targets are slabs of pure metal; a plasma knocks atoms off them, and the atoms settle on the wafer as thin metal films, including the barrier and seed layers for copper wiring ⁶. The copper wiring itself is then filled in by electroplating ⁷. Filters and carriers keep contamination out.

Variants and trade-offs

Each resist class is specific to one kind of lithography, such as EUV, ArF immersion, ArF, KrF or i-line ⁸.

Who makes it

CSET's January 2021 brief, citing a 2019 estimate, gave Japan 90 percent of the semiconductor photoresist market, with the rest largely held by US and South Korean firms ⁸. A separate Fuji Keizai survey, relayed in the December 2025 strategy deck of Japan's Ministry of Economy, Trade and Industry, measures sales by company nationality and puts Japanese companies at 77 percent in 2021 and 78 percent in 2023, with American and South Korean companies next ².

CSET's January 2021 brief lists JSR, Tokyo Ohka Kogyo, Shin-Etsu Chemical, Fujifilm and Sumitomo Chemical of Japan as resist makers, along with Dongjin of South Korea, the American firms DuPont, EMD Performance Materials and Inpria, and four Chinese firms ⁸. Qnity Electronics, the former DuPont electronics business, says in its 2025 annual report that it offers lithography materials for every wavelength, including extreme ultraviolet ⁹. In its 2025 annual report summary, the Chinese firm Hubei Dinglong said China had yet to reach large-scale production of advanced resist for 248 nm, 193 nm or extreme-ultraviolet printing, though three of its own resists for 248 nm and 193 nm printing had moved into stable volume supply ¹⁰.

A vehicle of Japan Investment Corporation, a state-backed fund, took 84.36 percent of JSR's shares at ¥4,350 each in a tender offer that closed on 16 April 2024 ¹¹. JSR's shares were delisted from the Tokyo Stock Exchange on 25 June 2024 ¹².

Tokyo Ohka Kogyo sold ¥139,668 million in the first half of fiscal 2026, up 25.1 percent, as strong demand for AI servers in data centers raised demand for chips ¹³. Fujifilm planned to raise its polishing-slurry capacity at Kumamoto by about 30 percent from January 2025 ¹⁴. It also scheduled new production and quality-evaluation equipment for extreme-ultraviolet resist at Shizuoka and Pyeongtaek to start in October 2025 ¹⁵.

Wafer fabrication materials sold $45.8 billion in 2025 and packaging materials $27.4 billion ¹⁶.

In electronic gases, CSET named Merck, Air Products and Air Liquide as the market leaders in January 2021 ⁸. Air Liquide's electronics arm alone sold €2,465 million in 2025, 9.1 percent of group revenue ¹. Smaller firms specialize in single molecules: SK Materials in nitrogen trifluoride, Kanto Denka in fluorine chemistry, Stella Chemifa and Morita in ultra-high-purity hydrofluoric acid.

CSET's January 2021 brief, drawing on 2019 market reports, put five firms at more than 60 percent of wet chemicals and DuPont and Cabot Microelectronics at about 56 percent of a $790 million market in polishing slurries ⁸. The same Fuji Keizai survey that METI relayed counts sales by company nationality, and it puts Japanese companies at 51 percent of polishing-slurry sales and 59 percent of high-purity cleaning-liquid sales in 2023, up from 49 percent of each in 2021 ². Cabot Microelectronics renamed itself CMC Materials in October 2020 ¹⁷. Entegris completed its purchase of CMC Materials on 6 July 2022 ¹⁸. DuPont separated its electronics business into an independent company, Qnity Electronics, on 1 November 2025 ¹⁹. Qnity sells polishing slurries and pads ²⁰. In sputtering targets for semiconductors, JX Advanced Metals puts its own share of the world market at about 65 percent as of fiscal 2026 ²¹.

The chokepoint

Supply at this stage has been disrupted three times since 2019, twice by governments and once by a war.

In July 2019 Japan put photoresist, hydrogen fluoride and fluorinated polyimide under individual export licenses for South Korea. It had supplied more than 90 percent of Korean imports of two of the three, and hydrogen fluoride exports fell 87.9 percent ²². Japanese photoresist exports to Korea did not fall, possibly in part because Japan allowed three-year bulk licenses for some resist sales in December 2019 ²². South Korea bought more hydrogen fluoride from the United States and Taiwan and more photoresist from Belgium, and production of all three chemicals rose inside the country ²². The same study found that Japanese hydrogen fluoride exports to the United States rose, which may mean some Japanese supply reached Korea by way of the United States ²². The rise in Korean output came both from Korean firms and from Japanese companies' affiliates in South Korea ²². Japan ended the individual licenses on 23 March 2023, when it put exports of the three chemicals to South Korea under its bulk export license system ²³.

In 2022 Russia invaded Ukraine, which supplied about 70 percent of the world's neon and 90 percent of the semiconductor-grade neon used by US industry ²⁴. Many chipmakers had added to their gas stockpiles after Russia annexed Crimea in 2014, and Samsung, SK Hynix, Renesas and Rohm reported adequate neon supplies from China ²⁴.

China's export controls fall on the metals. Beijing announced export licenses for gallium and germanium on 3 July 2023, in force from 1 August ²⁵. On 3 December 2024 it said it would in principle grant no licenses to export gallium, germanium, antimony or superhard materials to the United States ²⁶. On 9 November 2025 it suspended that ban until 27 November 2026 ²⁷. Under a trade deal set out by the White House on 1 November 2025, China also agreed to issue general licenses for exports of gallium, germanium and antimony for the benefit of US end users and their suppliers ²⁸.

In the United States, germanium goes mainly into fiber optics, infrared optics, semiconductors and solar cells, and radiation detectors ²⁹. Of the gallium used in the United States, 73 percent went into integrated circuits built on gallium arsenide or gallium nitride, and 26 percent into optoelectronic devices such as LEDs and laser diodes ³⁰. Germanium metal averaged $4,100 a kilogram in 2025 against $1,392 in 2023, and US imports of the metal fell 67 percent in 2025 because of China's ban ²⁹. The US Geological Survey estimated that a total Chinese ban on gallium and germanium exports could cut US GDP by $3.4 billion ³¹.

The slower risk is the European Union's proposed restriction on PFAS, the long-lived fluorinated chemicals. The five national authorities behind it, from Denmark, Germany, the Netherlands, Norway and Sweden, evaluated more than 5,600 comments and updated the proposal, which ECHA, the EU chemicals agency, published on 20 August 2025 ³². In March 2026 ECHA's two scientific committees backed an EU-wide restriction with targeted derogations, one in a final opinion and one in a draft, and their evaluation is due to finish by the end of 2026 ³³. These chemicals are everywhere in a fab: photoacid generators, etch gases, chamber liners, pump seals and filter membranes are all fluorinated. The updated proposal assessed options that would let electronics and semiconductor makers keep using PFAS where the risks can be controlled, and the European Commission will decide in consultation with the member states ³².

Key evaluation criteria

• Purity, in parts per trillion of metallic contamination, a million times finer than parts per million, which is the spec that keeps entrants out.
• Qualification lock-in: a resist or slurry is approved for one layer of one product at one fab, so switching costs are counted in tape-outs.
• Photon efficiency for EUV resists: how much light the resist absorbs sets the dose, the dose sets how many wafers an hour the scanner prints, and too few photons per dose set the defect rate, which is the case for metal-oxide chemistry.
• Transportability: bulk gases are often made on site at the fab, while specialty gases travel in cylinders and can be embargoed.
• Byproduct exposure: gallium is recovered mostly as a byproduct of processing bauxite ³⁰. Germanium comes from certain zinc ores and coal deposits, so supply of both depends on another industry's economics ²⁹.

Every transistor in an AI accelerator gets its shape from a machine one company builds. ASML sold 327 lithography systems in 2025, 48 of them extreme ultraviolet ¹. Nobody else makes EUV systems ².

How it works

The stencil is a photomask, the film is photoresist and the machine is a scanner (see Photomasks and pellicles).

The wafer is coated with photoresist, a film that changes wherever light touches it. The mask holds one layer of the circuit as a pattern of clear and dark areas, drawn four times larger than life. The machine shines light through the mask, shrinks the image four times with a lens, and lands it on the film. A wash then removes the film where the light hit, and the pattern is left standing on the wafer for the next machine to etch in or fill with metal. Then the film is stripped and the next mask goes in. A chip takes dozens of masks, one per layer.

How lithography prints a chip

1. 01Coat
2. 02Stencil
3. 03Shrink
4. 04Wash
5. 05Repeat

Paused

The wafer is coated with a thin film that changes wherever light touches it.

1. Coat. The wafer is coated with a thin film that changes wherever light touches it.
2. Stencil. A stencil, called a mask, holds the pattern for one layer of the chip, drawn four times larger than life.
3. Shrink. Light shines through the stencil, and a lens shrinks the image four times and lands it on the film.
4. Wash. A wash removes the film wherever the light landed, and the pattern is left on the wafer.
5. Repeat. The machine steps across the wafer, printing one patch at a time, each about the size of a postage stamp.

Simplified. The newest machines, which use extreme ultraviolet light, carry the image with mirrors in place of a lens.

The image from one mask covers a patch about 26 by 33 mm, so the wafer moves under the lens one patch at a time, close to a hundred patches per wafer. ASML's own throughput rating for an EUV scanner assumes 96 of them ⁴. Before the wafer is exposed, the machine measures alignment marks printed in earlier layers so the new layer lines up with them, and ASML rates the NXE:3400B's matched-machine overlay at 2 nm ⁴.

Finer lines need shorter light. The finest light now in use, at 13.5 nm, is stopped by glass and by air, so an EUV scanner works in a vacuum and uses mirrors instead of lenses, and its masks are mirrors too ⁵. The older machines use light more than fourteen times longer ³. The immersion type among them gains extra sharpness by filling the gap between lens and wafer with water ⁶.

When one exposure cannot draw a pattern finely enough, the layer is printed with two, three or four masks instead. Each extra pass costs a mask, machine time and a chance to misalign, and ASML says one EUV exposure per layer cuts masks and process steps and lowers cost ².

Variants and trade-offs

Deep ultraviolet

Deep ultraviolet (DUV) light comes from gas lasers: 248 nanometers from krypton fluoride (KrF), 193 from argon fluoride (ArF), shone through air or water ³. These tools still dominate by volume. Of ASML's 327 systems in 2025, 131 were ArF immersion, 78 KrF and 16 ArF dry, all deep ultraviolet, and another 54 were older i-line tools ⁷. The i-line tools use 365 nm light from a mercury lamp, and ASML says they print features as small as 220 nm ³. A DUV scanner costs roughly $60 million. DUV is the one tier with named competitors, Nikon and Canon, and ASML still holds above 80 percent of it ⁸.

Immersion is the contested tier, because without EUV a fab needs NXT:2000i-class scanners and several passes per layer to reach leading-edge logic, and that is the tier Dutch export licensing covers.

Extreme ultraviolet

The 13.5 nm light comes from shooting molten tin droplets from a generator and hitting each droplet twice, with a low-intensity pulse to flatten it and then a more powerful one that vaporizes it into plasma, a process repeated 50,000 times a second ³. Zeiss mirrors carry it to the wafer, and the largest are a meter across, smooth down to tens of picometers, a picometer being a thousandth of a nanometer ⁶.

Brighter light means more wafers an hour, and ASML ran the first 1,000-watt EUV source in April 2025 ². Its TWINSCAN NXE:3800E now ships at its full 220 wafers an hour, 37 percent better than the NXE:3600D ².

High-NA EUV

High numerical aperture (High-NA) raises the aperture from 0.33 to 0.55 and cuts the smallest printable feature from 13 nm to 8 nm ⁹. Its optics shrink the mask image four times in one direction and eight in the other, halving the patch of wafer one exposure covers and doubling the exposures per wafer ⁹. The second-generation TWINSCAN EXE:5200B runs at 175 wafers an hour, 60 percent above the EXE:5000 ².

Reuters puts a standard EUV tool at around $200 million and a High-NA machine at $350 to $400 million, prices ASML does not publish ⁸.

Intel and TSMC have chosen differently on High-NA:

• Intel Foundry says it uses High-NA in volume production for select layers of some Intel 18A products ¹⁰. It installed the first EXE:5200B ¹¹. By September 2026 it had run more than one million wafers on High-NA tools, a count that includes tool testing and research as well as volume production ¹⁰.
• TSMC waited, and now says it will use High-NA in high-volume manufacturing from 2030 ¹².

ASML recognized four EXE systems in sales in 2025 against two in 2024 ¹. In its 2025 annual report, filed in February 2026, ASML said it expected the platform to start supporting high-volume manufacturing in 2027 ¹³. On 8 September 2026 it announced with TSMC a move to 12-inch photomasks to remove stitching constraints, aiming for a pilot mask line by 2031 and 12-inch High-NA systems in production by 2033 ¹².

Who makes it

ASML took EUR 32.7 billion in net sales in 2025 at a 52.8 percent gross margin ¹, and in July 2026 raised its 2026 forecast to EUR 43 to 45 billion at 54 to 56 percent ¹⁴. It assembles more than it makes, listing 5,100 suppliers ¹³. Four of them make the main parts of the EUV machine:

• Zeiss SMT, Oberkochen, makes the illumination system and the six-mirror projection optics ¹⁵.
• Trumpf, Ditzingen, makes the carbon dioxide drive laser, which amplifies a few watts to 40 kilowatts ¹⁶.
• ASML San Diego, which includes the light-source maker Cymer that ASML bought in 2013, designs the source where the laser turns tin into plasma, and builds the droplet generator ¹⁷.
• VDL ETG builds the frames that suspend and position the mirrors ¹⁸.

ASML says the production capacity of Zeiss, its sole supplier of optics, limits how many lithography systems it can build ¹³.

Nikon and Canon are specialists now. Nikon sold 22 new chip lithography systems in the year to March 2026, into a market it sizes at 570 units for 2025, and its Precision Equipment business made an operating loss ¹⁹. Canon's alternative is nanoimprint, where the FPA-1200NZ2C stamps the pattern instead of projecting it, down to a 14 nm linewidth ²⁰. Canon delivered one in 2024 to the Texas Institute for Electronics, to be used for research and prototypes ²⁰.

Controls and China's answer

Export controls bar EUV from Chinese foundries ²¹. In September 2025, before the Chinese prototype described below was reported, CSIS judged that EUV remained "firmly out of reach" for China despite massive state investment ²¹. Below EUV, the restrictions arrived in this order:

• Dutch national licensing of advanced DUV took effect on 1 September 2023 ²².
• A US rule published on 25 October 2023 put certain immersion scanners bound for advanced chipmaking under US export rules if they held any American content at all, unless the country they were first exported from already controlled them ²³.
• A partial license revocation disclosed on 1 January 2024 stopped NXT:2050i and NXT:2100i shipments to a few Chinese customers ²⁴.
• The Netherlands widened its licensing from 7 September 2024 ²². On 15 January 2025 it announced that from 1 April 2025 the license requirement would also cover a very limited number of further goods, among them specific measuring and inspection equipment ²⁵.
• The BIS Affiliates Rule extended entity-list controls to affiliates owned 50 percent or more by listed entities from 29 September 2025 ²⁶, then BIS suspended it to 9 November 2026 ²⁷.
• The EU added certain Dutch controls to the EU Control List in November 2025, and ASML says this changed nothing for its immersion tools because they already needed a Dutch license ¹³.

China fell from 41 percent of ASML's net system sales in 2024 to 33 percent in 2025 ⁷.

On DUV, Reuters reported in July 2026, on one unnamed source, that Shanghai Aishengna Electronic Technology Group has started producing home-grown immersion DUV tools. The firm was registered in August 2023 with 7 billion yuan of capital and two state shareholders, Shanghai Electric Holding and a Shanghai International Trust subsidiary. It has no website, and has taken in teams from SMEE and the startup Yuliangsheng ²⁸. SMEE, the incumbent, is strongest in i-line and even there holds about four percent of the world market ²¹.

On EUV there is less evidence, and claims of Huawei mass production in 2026 remain unverified. Reuters reported in December 2025 that a Shenzhen team of former ASML engineers had built a prototype that makes extreme ultraviolet light but no chip ²⁹. Between that light and a printed chip sit the mirrors, and ASML's sole supplier of them is Zeiss ¹³.

The chokepoint

If ASML stopped shipping, no fab anywhere could add EUV scanners. Tools already in fabs would keep printing for as long as they were serviced. In its 2025 annual report ASML said about 95 percent of the systems it had sold in the previous 30 years were still in use ¹³. It guarantees service and spare parts for each platform until at least a committed date, subject to export controls ¹³. Even ASML could not rebuild itself quickly, since Zeiss makes its optics and Trumpf its drive laser.

In July 2026 ASML put its 2026 capacity at around 65 standard (low-NA) EUV scanners and said it plans to add 30 percent for 2027 ¹⁴.

For AI accelerators, EUV is the point of control. It prints the finest layers, the ones that set how densely transistors and wires pack, and TSMC expects the number of layers needing High-NA to rise as AI designs grow more complex ¹². Every added layer is more time on a tool nobody else builds.

Key evaluation criteria

• Resolution. Set by the Rayleigh criterion, which puts the smallest printable feature at k1 times the wavelength divided by the numerical aperture ³⁰. The factor k1 depends on the chipmaking process and has a physical limit of 0.25 ³⁰. 13 nm at 0.33 NA, 8 nm at 0.55 NA ⁹.
• Throughput. Wafers an hour at a stated dose. 220 on the NXE:3800E, 175 on the EXE:5200B ².
• Overlay. How precisely one layer lands on the one below; ASML says the EXE:5200B's improved projection optics, developed with Zeiss, maximize imaging and overlay ².
• Field size. The patch of wafer one exposure covers. High-NA halves it ⁹. ASML and TSMC plan 12-inch masks to remove stitching constraints ¹².
• Source power. Brighter light, more wafers an hour, which is why the 1,000-watt demonstration matters ².

Every EUV layer on an AI accelerator needs a flawless mask, built on a blank plate from one of only three suppliers worldwide, two of which are Japan's AGC and Hoya ¹. AGC says it is the only company in the world that takes an EUV blank all the way from the glass to the finished coating ².

How it works

How a photomask prints its pattern

1. 01The scanner
2. 02A mirror
3. 03The pattern
4. 04Wafer after wafer
5. 05One speck

Paused

A photomask is the stencil that lithography prints from, one for each layer of a chip. Inside the scanner, light bounces off the mask and carries its pattern down to the wafer.

1. The scanner. A photomask is the stencil that lithography prints from, one for each layer of a chip. Inside the scanner, light bounces off the mask and carries its pattern down to the wafer.
2. A mirror. No glass lets the short light now in use pass through. So the mask is a mirror, built up from about forty pairs of very thin layers laid on glass, and the light bounces off it.
3. The pattern. A dark pattern drawn on the mirror soaks up the light wherever no line should print. The light that bounces back carries the pattern of one layer.
4. Wafer after wafer. The same mask prints its layer on wafer after wafer, so one plate shapes millions of chips.
5. One speck. A speck of dust on the mask prints on every wafer, until someone finds it. The pellicle, a dust cover meant to protect the mask, is still short of production in a leading-edge fab.

Simplified. The mask is drawn face down, as it sits in the scanner. The mirror layers and the dark pattern are drawn far thicker than they are, and the light's path through the scanner's mirrors is cut to one bounce.

ASML says a chip's most complicated layers are made on EUV machines, while the rest can often be printed on older deep ultraviolet machines ³. A mask starts as a blank, a polished plate with nothing on it yet. For deep ultraviolet the blank is a window of quartz carrying a light-blocking film such as molybdenum silicide, and Shin-Etsu supplies those blanks ⁴. For EUV the blank is a mirror of about 40 molybdenum and silicon layer pairs, 7 nm to a pair, laid on glass, with a dark tantalum film on top, the absorber, that will carry the pattern ⁵.

The mask shop coats the blank with resist, and a mask writer draws the design into the coating with electrons. A single-beam writer flashes one shape at a time, while NuFlare's multi-beam writer for the most advanced masks controls 260,000 beams at once ⁶. A wash removes the drawn resist, an etch removes the blocking film or absorber wherever the resist is gone, and the rest of the resist is stripped. The plate now passes light, or reflects it, in the exact shape of one layer of the chip. On standard scanners it is drawn four times larger than it will print. An inspection tool compares the plate to the design, and a repair tool fixes the stray defects it finds.

Making the plate a mirror creates its own problems:

• Mask 3D effects. Light strikes the mirror at a slant, and the absorber has height, so its edges throw small shadows that distort the printed shape; software has to correct for it in advance.
• Write precision. Every edge of the absorber has to sit within a few nanometers of where the design says.
• Particles. Anything on the reflector prints on every wafer until someone finds it.

High-NA scanners, the newest EUV machines, print finer lines with larger mirrors. To keep masks at their usual size, their mirrors shrink the pattern four times in one direction and eight times in the other, so each exposure covers half the patch of wafer and a wafer takes twice as many exposures ⁷. On 8 September 2026 ASML and TSMC announced an initiative to move from today's 6-inch masks to 12-inch masks, which they expect to raise fab productivity, lower chipmaking costs and remove stitching constraints ⁸. They aim to set up a 12-inch mask pilot line by 2031, so that High-NA scanners using 12-inch masks can enter advanced chip production by 2033 ⁸.

Variants and trade-offs

Blanks

AGC says it invested more than a decade in meeting the blank's requirements, which include near-zero thermal expansion, perfectly smooth and flat surfaces and no particle contamination, and mass production only began in 2017 ¹. AGC publishes no share figure for EUV blanks, but it counts the suppliers. It says it is one of three companies worldwide that supply EUV blanks, and the only one that handles every material and process itself ¹. Its own data book ranks AGC No.2 worldwide in EUV lithography photomask blanks, based on AGC's fiscal 2026 estimates ⁹.

Hoya says its share of the mask blank market is exceptionally high, and that customers may gradually move toward multi-sourcing EUV blanks ¹⁰. In April 2023 AGC said its EUV blank capacity would grow by about 30 percent in 2025, on a line in Fukushima selected under a METI supply-chain program, and that it was aiming for more than ¥40 billion of sales in the business by 2025 ². In December 2024 AGC said its EUV blank sales had grown 50 percent in 2023 ¹. The sales reached ¥40 billion in 2024, a year ahead of the 2025 target, AGC reported in February 2025 ¹¹. In June 2026 AGC said they had declined in 2025 and were on a recovery track in 2026 ¹². In August 2026 AGC planned capacity expansions of 20 to 50 percent across EUV blanks, polishing slurry and lens materials for lithography tools, with no separate figure for the blanks, and mass production on the added capacity to begin in 2028 ¹³.

Writers

An electron-beam writer cuts the pattern into a sensitive coating on the blank. Multi-beam writers fire many beams at once, and Japan's NuFlare sells them for 3 nm node design rules ⁶. In September 2023 Intel called Austria's IMS Nanofabrication the established industry leader in the multi-beam mask writing tools that advanced EUV requires, and agreed to sell roughly 10 percent of it to TSMC at a valuation of about $4.3 billion ¹⁴. TSMC's subsidiary TSMC Development held that 10 percent at the end of 2024, at a fair value of $432.8 million in TSMC's accounts ¹⁵. Intel sold a combined 32 percent of IMS in 2023 and still held the other 68 percent on 27 December 2025 ¹⁶. Counting all electron-beam mask writers, CSET put IMS's share of a $994 million world market at 46.6 percent in 2025, ahead of NuFlare at 39.2 percent and JEOL at 14.2 percent ¹⁷.

Inspection and repair

A mask defect costs yield on every wafer that mask prints, so fabs check masks three times: as blanks, after patterning and again in production. Actinic inspection uses 13.5 nm light, the wavelength of EUV lithography, and Lasertec launched the world's first actinic EUV patterned mask inspection system, the ACTIS A150, in 2019 ¹⁸. In October 2025 it launched the ACTIS A200HiT series, which it says triples the A150's inspection speed ¹⁸. Lasertec reported net sales of JPY 230,485 million in the year to June 2026 ¹⁹. KLA sells optical reticle inspection tools for both EUV and optical masks ²⁰. Zeiss makes AIMS EUV, which checks a mask in EUV light under the scanner's own imaging conditions to judge how a defect will affect printing, and says it can be extended to ASML's High-NA scanner, the EXE:5000 ²¹. Zeiss also sells electron-beam repair tools that work on EUV masks ²².

Pellicles

A pellicle is a thin membrane on a frame above the mask. Particles land on it, too far out of focus to print, and the pattern below stays clean.

ASML's EUV membrane is 13 nanometers thick, has to hold together at 500 degrees Celsius in vacuum, and every photon it absorbs is light that never reaches the wafer ²³. ASML released its first EUV pellicles in 2016 and calls the pellicle one of the breakthroughs that brought EUV lithography to high-volume manufacturing ²³. The light crosses it twice, on the way in and on the way back off the mirror, so absorption counts double.

Carbon nanotube membranes are the next step, aimed at next-generation High-NA, high-output EUV scanners ²⁴. In 2020 imec mounted them on reticles and exposed them in an NXE:3300 scanner, measuring single-pass transmission up to 97 percent and finding the effect on imaging low and correctable ²⁵. Mitsui Chemicals, which began commercial production of silicon-based EUV pellicles under an ASML license in 2021, said in 2024 it would build a plant at Iwakuni-Ohtake, tentatively due to finish in December 2025, for carbon nanotube membranes with 92 percent or higher transmittance that withstand exposure power above 1 kW ²⁴.

Cost and design economics

In July 2022 SemiAnalysis put mask sets beyond $1 million at 28 nm and beyond $10 million at 7 nm, and expected 3 nm mask sets to push into the $40 million range ²⁶. Its May 2026 primer still puts a leading-edge mask set at $40 million, and a single respin, remaking a chip after a design flaw, at leading-edge nodes at $50 million to $100 million ²⁷.

That cost decides who can use a node at all. SemiAnalysis wrote that falling cost per transistor at 5 nm and 3 nm is limited to firms with large wafer volume, and that more companies will lack the volume to spread the fixed cost of mask sets ²⁶. It expected failed chip designs to show up first among AI chip startups, which work on much tighter budgets ²⁶.

Who makes it

Mask making splits between chipmakers that make masks for their own use and independent merchant firms that sell to them and others ²⁸. Photronics says the market was majority captive-supplied for a period, and that production has more recently tended to move toward the independents ²⁸. Photronics, a leading worldwide maker of IC and flat panel display masks, had $849.3 million of fiscal 2025 revenue, of which $615.1 million was IC masks ²⁹. Its named competitors in chip and display masks include Dai Nippon Printing, Hoya, Tekscend Photomask and two Chinese firms, Shenzhen Newway Photomask and Shenzhen Qingyi Photomask, and it also competes with chipmakers' own mask shops ²⁸.

SMIC runs two in-house mask shops in Shanghai, for g-line, i-line, DUV and ArF steppers and scanners ³⁰. Photronics began operating two mask plants in China, in Hefei and Xiamen, in 2019, and its chip mask business in Xiamen is a joint venture in which DNP holds 49.99 percent ²⁸. There is no Chinese EUV blank, no Chinese actinic inspection tool and no Chinese multi-beam writer.

The chokepoint

Mask blanks are a small, highly concentrated business. Three firms supply EUV blanks worldwide, AGC says, and AGC spent more than a decade meeting the blank's requirements before mass production began in 2017 ¹. AGC said in June 2026 that its EUV blank sales reached ¥40 billion in 2024, declined in 2025 and were recovering in 2026 ¹². Lasertec launched the first tool that inspects patterned EUV masks in EUV light, in 2019 ¹⁸.

Pellicles already work in high-volume EUV manufacturing, but ASML says no material is completely transparent to EUV light, so any pellicle in the light's path costs customers productivity ²³. In 2024 Mitsui Chemicals said it would set up production of carbon nanotube membranes for next-generation High-NA, high-output EUV scanners ²⁴.

Key evaluation criteria

• Blank defectivity. Particles buried in the multilayer cannot be repaired, so blank yield sets mask yield.
• Write time and placement. Intel said in 2023 that advanced EUV requires multi-beam mask writing tools, and called IMS the established industry leader in them ¹⁴. In 2025 IMS held 46.6 percent of the market for all electron-beam mask writers, on CSET's count ¹⁷.
• Actinic inspectability. A 13.5 nm inspection uses the same wavelength as EUV lithography, and Lasertec launched the first one for patterned masks in 2019 ¹⁸.
• Pellicle transmission and lifetime. Transmission counts twice, and imec measured carbon nanotube membranes passing up to 97 percent in a single crossing in 2020 ²⁵.
• Mask-set cost per node. In July 2022 SemiAnalysis put a set above $10M at 7 nm, a cost that decides which designs can use a node ²⁶. In May 2026 it put a leading-edge set at $40M ²⁷.

Applied Materials and Lam Research, the two largest deposition and etch suppliers, booked $28.4 billion and $23.2 billion of revenue in their latest fiscal years ^{1 2}.

How it works

One round of deposition and etch

1. 01The wafer
2. 02Deposit
3. 03Coat
4. 04Expose
5. 05Develop
6. 06Etch
7. 07Strip
8. 08Repeat

Paused

A slice through one spot on a wafer, magnified until its layers show.

1. The wafer. A slice through one spot on a wafer, magnified until its layers show.
2. Deposit. A film a few atoms thick is laid over the whole wafer.
3. Coat. A light-sensitive coating, the resist, is spun on top.
4. Expose. Light shines through a stencil and changes the resist wherever it lands.
5. Develop. A wash removes the resist the light reached, leaving the stencil’s pattern.
6. Etch. A plasma cuts straight down through the film wherever the resist is gone.
7. Strip. The leftover resist is removed. The pattern now sits in the film.
8. Repeat. Insulator fills the gaps and the next layer goes on. A chip takes more than a thousand of these rounds.

Simplified cross-section. The layers are drawn much thicker than they are.

Most etch steps, and many deposition steps, happen in a vacuum chamber that holds one wafer at a time. A pump empties the chamber of air, a measured flow of gas comes in, and an electric field that reverses millions of times a second, a radio-frequency field, turns the gas into a plasma. The field splits the gas into charged ions and into neutral fragments called radicals, which are more reactive than whole molecules ⁵. Batch furnaces such as Tokyo Electron's TELINDY PLUS instead heat as many as 125 wafers at once, usually without plasma, for oxidation, low-pressure chemical vapor deposition and some atomic layer deposition ⁶.

For deposition the gas carries the material wanted. The molecules, or the radicals a plasma splits from them, land on the wafer and stick, and the film builds from the bottom up, a few atoms at a time. To coat the floor of a deep hole as thickly as its rim, the machine can work in cycles: let one gas settle in a single layer on every surface, pump it out, admit a second gas that reacts with that layer and nothing else, pump again. Each cycle adds a fraction of a layer of atoms wherever the gas reached, so the film builds up as evenly on the walls and floor of a hole as on its rim ⁷.

For etch the gas attacks one material and leaves the one beside it. Wherever the photoresist pattern covers the wafer, nothing happens. Wherever it does not, the radicals react with the surface and turn it into a gas, which the pump carries away. A second field pulls the ions straight down at the wafer, so the etch cuts vertically and a narrow hole keeps its width as it deepens ⁵. When the etch reaches the material underneath, which the gas was chosen not to touch, it slows almost to a stop, and the tool ends the step.

Deposition and etch chambers are separate products built from similar vacuum, gas and radio-frequency parts, and the export controls describe each tool by the process it is designed to run ⁷.

A part-finished chip can cross international borders 70 or more times on its way to the end customer, a 2020 estimate by Accenture and the Global Semiconductor Alliance that the Semiconductor Industry Association repeated in 2025 ³.

Variants and trade-offs

Deposition families

The market sizes and leading shares below are CSET's for 2025, which it builds from TechInsights data, on a $26.2 billion deposition tool market ⁸ and a $21.9 billion dry etch market ⁹.

• Physical vapor deposition knocks atoms off a solid target and lands them on the wafer, $4.9 billion in 2025 ¹⁰.
• Chemical vapor deposition reacts gases at the wafer surface to grow a film; the plasma-enhanced version runs cooler and is most of the $11.2 billion CVD market, $7.5 billion in 2025 ^{11 12}.
• Atomic layer deposition lays down less than one atomic layer at a time, so it coats vertical walls as evenly as horizontal floors. US regulators call it a 3D scaling enabler in 3D DRAM, 3D NAND, and FinFET and gate-all-around logic ⁷; ASM International leads it with 54.5 percent of a $4.1 billion market in 2025 ¹³.
• Epitaxy grows layers that line up with the crystal beneath them, using high-temperature CVD tools ¹⁴. Electroplating deposits the copper used for wiring across the wafer ¹⁵.

Etch families

• Conductor etch cuts gates, metals and silicon, $12.2 billion in 2025, led by Lam at 51.2 percent ¹⁶.
• Dielectric etch cuts the insulating oxides and nitrides between them, $8.7 billion in 2025, led by Tokyo Electron at 55.9 percent ¹⁷.
• High-aspect-ratio etch cuts the deep, narrow channels that let 3D NAND stack layers of memory cells, and Lam says slight deviations from the target profile can hurt yield ⁴. Lam runs the etch well below 0 degrees Celsius and says Cryo 3.0 holds critical-dimension deviation under 0.1 percent down channels up to 10 microns deep ⁴.

AI hardware asks for sideways cuts, deeper holes and a second metal stack on the wafer's back.

• Gate-all-around needs highly selective isotropic etch, which cuts sideways, and BIS controls isotropic dry etch tools with a silicon-germanium-to-silicon selectivity of 100:1 or more ⁷.
• HBM needs holes etched straight through the silicon so chips can be stacked and wired, which BIS controls at 10:1 or deeper above 7 microns a minute ¹⁸.
• Backside power delivery moves power routing to the back of the wafer ¹⁹. Applied Materials expects it to add another $1 billion per 100,000 wafer starts a month to the wiring market it serves ²⁰.

Who makes it

SEMI put global equipment billings at $135.1 billion in 2025, up 15 percent from $117.1 billion, with wafer processing equipment up 12 percent ²².

Within deposition and etch no one firm dominates as ASML does in lithography. The share chart in Tokyo Electron's own results presentation puts it at 23 percent of dry etch, 27 percent of deposition systems (furnace, ALD and low-pressure CVD tools) and 15 percent of ALD in 2025, against 91 percent of coater/developer ²¹.

ASM International, the atomic layer deposition specialist, reached a record EUR 3.2 billion of revenue in 2025 as customers built 2 nm gate-all-around capacity, with molybdenum ALD entering volume production ²³.

China and the controls

China is the tool vendors' largest market, and Chinese toolmakers have gained share since 2019 ²⁴. It bought $49.3 billion of equipment in 2025, still the biggest single market, though its spending fell half a percent while Taiwan's rose 90 percent to $31.5 billion ²². China still takes a large share of every major vendor's sales.

• Tokyo Electron: 34.1 percent of sales in the year to March 2026, down from 41.7 percent ²¹.
• Lam Research: 26 percent in the June 2026 quarter, behind Taiwan at 27 percent ².
• Applied Materials: 28 percent in the third fiscal quarter of 2026, down from 35 percent ²⁵.
• ASM International: more than 30 percent of 2025 revenue ²³.

Between 2019 and 2024 China-based suppliers went from 2 to 7 percent of deposition and from under 3 to almost 9 percent of etch and clean, and in ALD they gained no share and held less than 1 percent in 2024 ²⁴. CSET's newer analysis of TechInsights data published in July 2026 puts them at 9.8 percent of deposition in 2025 ⁸. They held 10.1 percent of etch and clean that year ²⁶. In dry etch alone their share was 12.4 percent ⁹. In ALD they held 2.6 percent in 2025, most of it from Piotech ¹³. AMEC by itself held 12.4 percent of dielectric etch in 2025 ¹⁷. AMEC turned over RMB 12.385 billion in 2025, up 36.6 percent, and spent RMB 3.744 billion on research, 30.2 percent of sales ²⁷.

Washington tightened these rules at least five times between 2022 and 2025.

• October 2022. The 7 October interim final rule put certain chipmaking equipment and some US person support under license and widened foreign-produced item rules for 28 listed Chinese entities ²⁸.
• October 2023. The rule effective 17 November rewrote the equipment entries, adding isotropic and anisotropic dry etch (ECCN 3B001.c.1), spatial ALD (3B001.d.9), low-fluorine tungsten ALD and CVD (3B001.d.10) and carbon hard mask PECVD (3B001.d.5) ⁷.
• December 2024. BIS controlled 24 more types of equipment and three types of software, added 140 entities and wrote a foreign direct product rule that reaches some tools built outside the United States ²⁹. The new entries take in TSV etch and deposition into features with aspect ratios above 200:1 ¹⁸. The rule largely exempts foreign-made tools exported by firms located in Japan, the Netherlands and the 31 other countries it lists, whose governments can control these tools themselves ¹⁸. Japan added advanced chipmaking equipment to its control list on 23 July 2023 ¹⁸.
• September 2025. BIS removed the Chinese units of Samsung and SK hynix, and Intel Semiconductor (Dalian), from the Validated End-User program, effective 31 December 2025, so US tools bound for them now need a license ³⁰. BIS estimated that the change would add 1,000 license applications a year ³⁰.
• September 2025. The Affiliates Rule extended Entity List restrictions to any company at least 50 percent owned by a listed entity ³¹; BIS then stayed it to 9 November 2026 ³².

Applied Materials took a $253 million charge to settle an export controls compliance matter with BIS, so the rules reach the vendors as well as their customers ²⁵.

Of the tools in the chart below, China's share is largest in dry stripping, a $314.6 million market in 2025, where Mattson Technology held 22.6 percent and Naura 8.3 percent ³³. Mattson is a US-based firm that Beijing E-Town bought in 2016 ²⁴.

The chokepoint

The chokepoint is real but weaker than lithography's. Three or four credible vendors exist for most deposition and etch steps, and atomic layer deposition has at least five, led by ASM International at 54.5 percent in 2025 ¹³. China's own toolmakers held only 2.6 percent of atomic layer deposition in 2025 ¹³. The December 2024 rule targets advanced atomic layer deposition tools and the extremely deep, narrow holes that HBM and 3D memory need ¹⁸.

Key evaluation criteria

• Selectivity. How hard the process attacks one material and spares another. BIS controls wet processing at a silicon-germanium-to-silicon ratio of 100:1 ⁷.
• Conformality and aspect ratio. Whether a film reaches the bottom of a hole, and how deep that hole is against its width. Controls start at 10:1 for TSV etch and 200:1 for 3D DRAM deposition ¹⁸.
• Uniformity. Variation across a 300 mm wafer, with the TSV etch control set at within-wafer etch depth nonuniformity of 2 percent or less ¹⁸.
• Throughput. Wafers per hour, which sets cost per layer and decides how many lots a fab can run.
• Particles and chamber matching. How large a share of the defects a fab can tolerate comes from these tools, and whether one chamber behaves like the next, which metrology and inspection measure (see Metrology and inspection).

Process control tools were a $15.7 billion market in 2025 ¹. KLA puts the whole wafer equipment market, including advanced packaging, at about $120 billion that year ². CSET's count for 2025, built on TechInsights data, puts KLA at 56.8 percent, about five times Applied Materials' 11.2 percent ¹. At its March 2026 investor day KLA cited Gartner's figures for 2024, which put its share at 56.5 percent, 6.5 times its nearest competitor ³. In April 2026 KLA said its 2025 share was about 7 times the nearest competitor's ⁴. The figures rest on different data and years, so the multiple runs from about 5 to about 7.

How it works

An inspection tool sweeps a beam of light across the wafer, photographs it, and compares the image of each chip with the image of its neighbors. The chips on a wafer are meant to be identical, so anything that shows in one and not the others is a defect, and the tool records where it is. For faults too small for light to show, a second tool scans a beam of electrons across a small patch and builds a picture from the electrons that bounce back.

A metrology tool measures known shapes. It shines light on a test pattern printed beside the circuits and works out from the scatter how wide the lines are and how thick the film is, and it reads marks printed in this layer and the last to measure how far the two are out of line, which is overlay.

The fab pays for all this to protect yield, the share of chips on a wafer that work. A wafer loses value two ways: whole regions ruined by mishandling, misalignment or over-etching, and single circuits killed by stray material or an airborne particle ⁵.

A bigger chip is a bigger target for the second kind, and the loss grows faster than the area. In the standard formula, die yield is (1 + D0A/a) to the power minus a, where D0 is defects per square centimeter, A is die area and a is a clustering constant of 3 to 4, which says how much defects bunch together. At a defect density of 0.8 per square centimeter, with a set to 3, a 1 square centimeter die yields 49.2 percent and a 2 by 2 centimeter die 11.3 percent, so the bigger die, which also fits fewer times on a wafer, costs 20.1 times as much ⁵.

Run that equation with a clustering constant of 3 for an 8 square centimeter die, about as much as one exposure can print, and it yields about 49 percent at a defect density of 0.10 and about 69 percent at 0.05 ⁵. Getting from one to the other is yield learning, which means finding the process step that is losing dies and fixing it.

Those percentages are the share of dies with no killer defect. A chip built from many identical blocks can carry spares and switch off a faulty block ⁵. Nvidia's full H100 design has 144 of its main computing blocks, called streaming multiprocessors, and the SXM5 version it ships has 132 turned on ⁶. So the share of dies that can be sold is higher than the formula gives. What the formula shows is how fast flawless dies get scarce as chips grow.

Why big chips lose more to defects

1. 01Specks land
2. 02Small chips
3. 03AI-size chips
4. 04Half the specks

Paused

Specks of dust and tiny flaws land at random on every wafer.

1. Specks land. Specks of dust and tiny flaws land at random on every wafer.
2. Small chips. Cut into small chips, almost every chip misses every speck.
3. AI-size chips. An AI chip covers eight times the area, so about half of them catch a speck and fail.
4. Half the specks. Halve the specks and about seven in ten AI chips work. Finding defects pays most on the biggest chips.

Simulated 300 mm wafer: 68 specks, 0.10 per square centimeter, placed at random in loose clusters. The share of flawless chips follows the formula above with a clustering constant of 3.

Variants and trade-offs

The tools trade sensitivity against speed. All the market sizes and shares below are CSET's, for 2025 ¹.

• Defect inspection scans a whole wafer with light or electrons and compares each die against its neighbors. It is by far the largest family, $6.7 billion, and the one KLA dominates, at 85.9 percent. ASML's HMI eScan 1100 runs 25 electron beams at once, up to 15 times the throughput of single-beam inspection tools, and finds patterning defects down to 7 nm ⁷.
• Film and shape metrology measures how thick each film is and how flat the wafer sits, without cutting it open: $2.6 billion, with KLA at 45.6 percent, Nova at 24.6 and Onto Innovation at 10.9. Onto paid about $720 million in August 2026 for 27 percent of Japan's X-ray maker Rigaku ⁸.
• Mask inspection and repair gets its own tools, because a defect on a mask repeats on every die: $2.2 billion, and one of two families where KLA has a close rival, 45.9 percent against Lasertec's 42 and Zeiss's 10.1. Lasertec also makes actinic inspection tools, which check EUV masks with the same 13.5 nm light that prints them, and it calls its ACTIS A150 the world's first EUV patterned mask inspection system ⁹. KLA's own actinic mask inspection tool was still at an early demo stage at its March 2026 investor day ³.
• Overlay metrology measures whether this layer sits on the one below: $991.4 million, split almost evenly between KLA at 51.5 percent and ASML at 47.9.
• Critical dimension metrology measures how wide a printed feature actually came out: $1.2 billion, and the one family Japan leads, with Hitachi at 71.9 percent and Applied Materials at 27.5.
• Electron-beam metrology resolves detail too fine for light: $1.3 billion, led by Applied Materials at 45.1 percent with ASML at 35.6 and KLA at 18.8.

Who makes it

KLA held 56.8 percent of a $15.7 billion market in 2025 ¹. KLA says its share grew 3.6 percentage points from 2021 to 2025 ⁴. Its fiscal 2026 revenue was $13.579 billion, after $12.156 billion in fiscal 2025 ¹⁰, and it says it gained share again in 2025 across mask, optical wafer and e-beam inspection ⁴.

The rest are specialists, and none holds more than 11.2 percent, by CSET's count for 2025 ¹.

• Applied Materials is the largest of them at 11.2 percent, selling e-beam defect review, CD-SEM line-width tools and e-beam metrology next to the deposition and etch tools that create the defects.
• Lasertec holds 6.4 percent, almost all of it mask inspection; Hitachi High-Tech 6.2 percent, most of it CD-SEM; ASML 5.9 percent through YieldStar overlay and HMI e-beam metrology.
• Nova holds 4.3 percent, through film metrology, and took $880.6 million of revenue in 2025 ¹¹.
• Onto Innovation holds 2.6 percent on $1,005.3 million of 2025 revenue ¹² and Camtek 1.6 percent on $496.1 million ¹³.

Patterning, which includes metrology products and reticle inspection, grew 61 percent year on year in the June 2026 quarter, when Taiwan took 31 percent of KLA's revenue and China 26 percent ².

Process control's share of fab spending is still rising, and in memory KLA credits higher performance specifications, less redundancy and more logic content in devices built for high-performance computing ⁴.

KLA's systems also apply AI-driven analytics and noise suppression, and KLA says it has added AI capabilities across its entire product portfolio over the past five years ⁴.

Packaging, AI and China

The AI build-out is increasing the importance of advanced packaging and of the process control it needs ². KLA took the number one position in advanced wafer-level packaging process control in 2025, adding 14 points ⁴, and expects about $1.1 billion of packaging process control revenue in 2026, more than 70 percent growth ². Onto signed a volume purchase agreement estimated at over $240 million with an HBM maker for 2D inspection and 3D bump metrology through 2027 ¹².

Chinese makers are still small in process control, but one of them is growing fast. CSET's count, built on TechInsights data, puts all Chinese firms at 0.7 percent of a $15.7 billion market in 2025 ¹. Skyverse (Shenzhen Zhongke Feice), which makes wafer inspection and metrology tools, reported 2.05 billion yuan of revenue in 2025, about $285 million, up 48.75 percent on 2024 and more than double its 2023 revenue ¹⁴. That alone is about 1.8 percent of CSET's market, more than twice CSET's figure for all Chinese firms, so the CSET count may miss some domestic sales ¹. In its 2025 annual report Skyverse says Chinese makers still hold a low share of China's market for these tools and that KLA holds the largest share of it ¹⁴. By CSET's 2025 count, Chinese firms held 0.6 percent of defect inspection tools ¹⁵. They held 0.4 percent of line-width measurement in 2025 ¹⁶. In film and shape metrology they held 2 percent in 2025, all of it from Raintree Scientific Instruments, or RSIC ¹⁷. They held no share of photomask inspection and repair tools in 2025 ¹⁸. Nor did they hold any share that year of the tools that inspect wafers during advanced packaging ¹⁹.

In October 2022 the US began requiring a license for any US-made item, process control tools included, bound for a Chinese fab that made logic chips at 16/14 nm or below, NAND memory with 128 or more layers or DRAM at 18 nm half-pitch or below ²⁰. The December 2024 rule added specific process control tools to the export lists. It controls defect inspection and measurement of patterned 300 mm wafers where the tool can find defects of 21 nm or smaller using light below 400 nm, or an electron beam resolving 1.65 nm, or a cold field emission source, or two or more beams ²¹. The same rule controls overlay metrology accurate to 0.5 nm or better that is built into the track, the machine that coats and develops the light-sensitive resist, or that can switch wavelengths quickly, and stand-alone wafer shape metrology that feeds corrections to immersion or EUV scanners ²¹. A separate new entry, 3B994, covers optical film and line-width metrology for 300 mm wafers with software for measuring non-planar transistors ²¹. BIS placed these tools in new entries for items it says also have legitimate uses in older chipmaking, so they carry narrower license requirements than tools built only for advanced chips ²¹. A new foreign direct product rule extends US jurisdiction to specified foreign-made chipmaking tools bound for Macau or for a Country Group D:5 destination such as China ²².

The chokepoint

Process control is a chokepoint of concentration. Several firms can build a good film metrology tool, but one firm leads most kinds of process control tool, and its share is still growing. A fab that can buy scanners and etchers but not sensitive inspection tools finds fewer of the defects that lower its yield, so its yield rises more slowly.

Key evaluation criteria

• Sensitivity. The smallest killer defect a tool can find. ASML's multibeam system is specified to 7 nm patterning defects ⁷.
• Throughput. Wafers per hour, which decides how many lots a fab can afford to look at; multibeam gives up to 15 times the throughput of single-beam tools ⁷.
• Nuisance rate. The share of flagged events that turn out not to be real defects, which is what AI classification is meant to reduce.
• Sampling plan. How many wafers and sites per lot, a cost decision as much as a physics one, which sets what process control costs the fab.
• Time to result. How fast a measurement reaches the process engineer, which sets the speed of yield learning.

A Blackwell GPU is 208 billion switches on two dies, each the largest a lithography machine can print in one shot ¹. Every switch has to turn on fully, turn off completely, and keep doing it for years. Making the switches is the front end of line; wiring them together is the back end.

How it works

Why the gate wraps around the channel

1. 01Inside a chip
2. 02On
3. 03Off, leaking
4. 04Fin
5. 05All around

Paused

An AI chip does all its work with transistors, tiny switches built into the silicon: 208 billion of them in one Nvidia Blackwell GPU. Making the switches is the front end of the factory; wiring them together comes after.

1. Inside a chip. An AI chip does all its work with transistors, tiny switches built into the silicon: 208 billion of them in one Nvidia Blackwell GPU. Making the switches is the front end of the factory; wiring them together comes after.
2. On. Each one is a switch. Seen end on, current flows through a strip of silicon, the channel, and the gate sits on top.
3. Off, leaking. Switching off, the gate squeezes the flow shut, but only near itself. In a tiny transistor, current still leaks through the part it cannot reach.
4. Fin. Stand the channel on edge as a fin, and the gate covers three sides. Much less gets through.
5. All around. Split it into thin sheets and wrap the gate around every side, and it shuts tight. That lets the switches keep shrinking, and smaller switches, packed tighter, are what make each new chip faster.

Simplified. The channel is seen end on, cut across the gate, with current drawn as points of light. Not to scale.

The front end builds that valve in a fixed order. First it marks where each transistor will sit and fires atoms of boron or phosphorus into the silicon there, a step called ion implantation, so that those patches conduct the way the design needs.

Next it shapes the channel, in a FinFET by etching the silicon into thin fins standing up from the wafer and laying the gate over the top and both sides of each fin, three sides instead of one. In a gate-all-around transistor the fab instead grows alternating layers of silicon and silicon-germanium, cuts the stack into a narrow bar, then dissolves the silicon-germanium away, leaving thin silicon sheets held at their ends like shelves, and fills the gaps above, below and beside each sheet with gate metal, all four sides. Before the metal goes in, a film of insulator a few atoms thick is laid over every sheet, so that the gate controls the channel without touching it. Last come the contacts, small metal plugs down to the two ends of the channel and to the gate, ready for the wiring layers above.

Each of those is a deposition, an etch or an implant of its own, and they have to run in exact order, since a sheet cannot be wrapped once the metal is on, nor the insulator added once it is buried.

Current leaks two ways, straight through the gate insulator and along the channel from end to end while the gate is off. The second is called short-channel leakage, and wrapping the gate around the channel reduces it. Three fixes deal with the two leaks:

• Better insulator. A thicker hafnium-based film, paired with a metal gate, lets fewer electrons slip straight through yet controls the channel as tightly as before. Intel replaced silicon dioxide with it at 45 nm in 2007 and said it cut leakage through the insulator more than tenfold and, with the metal gate, leakage along the channel more than fivefold ².
• More gate. Wrap gate metal around more sides of the channel, as fins and nanosheets do.
• Thinner channel. Thin the silicon until no current can flow where the gate cannot reach it.

Variants and trade-offs

Planar and FinFET

A planar transistor lays the gate on one side of a flat channel, and loses control as the channel shortens. A fin stands the channel on edge so the gate covers three sides, but current then comes in whole fins: a designer who needs more adds one, and nobody gets half a fin.

Gate-all-around nanosheets

A nanosheet lays the channel back down, stacks two to four thin sheets and threads gate metal around each one. The sheets can be drawn at different widths, so current comes in fine steps again. TSMC sells this as NanoFlex, which lets designers mix short cells for small area with tall cells for performance ³.

N2 entered volume production in the fourth quarter of 2025, TSMC's first nanosheet node ⁴. TSMC rates the follow-on N2P at 18 percent more speed at the same power, 36 percent less power at the same speed, and 1.2 times the logic density of N3E ⁵. Intel's RibbonFET shipped on 18A, and 18A-P adds another 9 percent performance at the same power ⁶. Samsung began initial production of its 3 nm gate-all-around process in June 2022, more than three years before TSMC's N2 ⁷.

Those numbers are vendor claims until someone measures the silicon. Each foundry picks its own baseline, and none publishes a density figure that can be set against a rival's.

Backside power delivery

Power and signal share one stack of copper wiring above the transistors, where wide power rails crowd out the signal wires. Backside power grinds the wafer thin and builds a second network underneath it.

Intel shipped it first as PowerVia: on 18A, an 11 percent cut in routed area and a tenfold cut in dynamic voltage droop, the sag in supply voltage when a block of logic switches on at once ⁶. TSMC's Super Power Rail lands that network straight on each transistor's source and drain, with no buried rail between, which is harder to build and gives more: against N2P, A16 gives 8 to 10 percent more speed, 15 to 20 percent less power and up to 1.10 times the chip density ⁵.

TSMC said in April 2026 that A13, a direct shrink of A14 with 6 percent area savings, and A12, which adds Super Power Rail to the A14 platform, are both scheduled to enter production in 2029 ⁸.

CFET and what comes after

A logic gate needs two transistors that switch on opposite signals, and today they sit side by side. The research institute imec sees complementary FETs, which stack the two on top of each other, as an attractive design for logic nodes beyond 1 nm ⁹.

The back end of line

Wiring is now as hard to make as the transistor. Copper seeps into the insulator around it, so every wire needs a barrier, a liner and a cap, and as the most critical wiring levels drop below a 20 nm pitch those extra layers take a large share of the wire's width ¹⁰. Two metals are moving into those narrow levels.

• Ruthenium shows promise for use without a barrier, which would keep the wire's resistance low ¹⁰. imec has demonstrated ruthenium lines at a 16 nm pitch ¹¹.
• Molybdenum conducts worse in bulk, 5.3 against copper's 1.68 microhm-cm, but in a thin film it beats tungsten by up to 30 percent and needs no barrier either, which is moving it into some contacts and local wiring layers ¹².

Who makes it

TSMC, Intel and Samsung build gate-all-around nodes with extreme ultraviolet lithography. SMIC builds 7 nm-class nodes without it ¹³. In July 2025 state-backed Rapidus said it had started making 2 nm prototypes at its plant in Chitose, Hokkaido, and would begin mass production in 2027 ¹⁴. By June 2026 it had raised 424.95 billion yen in equity, the latest 150 billion yen from a state agency, and it has received government research subsidies since fiscal 2022 ¹⁵.

Node names describe nothing physical. SMIC's N+3, its third-generation 7 nm process, sets its narrowest wires 32.5 nm apart, tighter than Intel 18A's 36 nm, and reaches 113.4 million transistors per square millimeter against 107.7 for TSMC's N6 ¹³.

AI accelerators have usually trailed the leading edge, since a very large die comes out working reliably only on a process that has run for years. Blackwell uses a custom TSMC 4NP ¹. AMD's MI455X, launched on 23 July 2026, lists TSMC 2 nm and 3 nm silicon ¹⁶. It spreads its compute across eight separate dies ¹⁷.

SRAM, the fast memory on the logic die, is the scaling failure that hurts AI chips most. TSMC claims 22 percent more SRAM density from N3E to N2, but the gain comes mostly from the circuits around the array, and the cell that holds one bit shrinks little or not at all ¹⁸. See Memory and HBM.

The chokepoint

No single machine makes the front end a chokepoint. The recipe does, and a recipe is which steps run in which order on which tools. In September 2024 the United States put a worldwide license requirement on the know-how for building gate-all-around transistors, with an exception for countries that impose matching controls ¹⁹.

China shows what that recipe costs. The third National Integrated Circuit Fund launched in May 2024 with 344 billion yuan, about $47 billion ²⁰, so money is not the constraint; tools are. A Shanghai state firm began building domestic immersion scanners in 2026 and planned about five that year and roughly 20 in 2027 ²¹. Those are deep-ultraviolet machines, a generation behind EUV, and SMIC gets fine features out of them by printing its tightest layers in several passes. That volume keeps those lines running and comes nowhere near replacing ASML. EUV is further away: China has announced $43 billion for domestic development, and the Center for Strategic and International Studies judged in September 2025 that EUV remains firmly out of reach despite massive state investment ²².

See Lithography and Geopolitics.

Key evaluation criteria

• Electrostatic control. How far the gate wraps the channel. It sets how much the switch leaks when off, and the lowest supply voltage it can run on.
• Density. Transistors per square millimeter, comparable only inside one foundry's own numbering and for one kind of cell.
• Interconnect resistance. Below a 20 nm wire spacing, copper wiring adds more and more delay from its resistance and capacitance ¹¹.
• Power delivery. The voltage lost carrying power across the die. Backside power frees area and cuts the droop tenfold ⁶.
• SRAM scaling. The cell that holds one bit has barely shrunk since the 5 nm node, which caps how much cache an accelerator can afford ¹⁸.
• Cost per transistor. No foundry publishes wafer prices, so it cannot be worked out from public figures.

TSMC calls a plant a GIGAFAB once it can run more than 100,000 wafers a month, each a 300 mm disc, twelve inches across ¹. It operates six of them, and every one is in Taiwan ².

How it works

Inside, the work is one loop repeated for every layer. Wafers travel in a lot, a batch of 25 in a sealed pod called a FOUP that only a machine opens. An overhead track carries the pod from tool to tool. At each tool a robot lifts one wafer out, the tool does its one job, depositing a film, printing a pattern, etching it, cleaning it or measuring it, and the robot puts the wafer back. The pod moves on to the next tool, often across the building, and the loop starts again with the next layer. A chip takes hundreds of those visits, so a wafer spends months inside.

The pod keeps the wafer clean for all of that time, because the wafer never meets the room's air, and even that air is filtered until it carries almost no dust. Every design in the building runs on the same tools because each tool is set by recipe, the list of gases, temperatures and times for one step, and a foundry offers each customer the same list of recipes on shared machines. The tools run day and night, since an idle tool earns nothing. The finished wafer is tested (see Test and assembly), then cut and packaged.

TSMC, founded in 1987, pioneered the pure-play model, in which a foundry makes only its customers' products ³. In 2023 BCG estimated that a new fab for chips at 2 nm and below, completed in 2026, would cost $35 to $43 billion to own over ten years, 33 to 66 percent above 2023 costs ⁴. In March 2026 the Semiconductor Industry Association told the US Senate that building and equipping a leading-edge fab takes as much as $20 to $25 billion of capital ⁵.

Every plant TSMC and its subsidiaries run came to more than 17 million wafers a year in 2025, counted as if each were the standard 12-inch size ². The six largest plants, called gigafabs, had a combined capacity of more than 13 million ¹. All six are in Taiwan, and the other plants are five smaller fabs in Taiwan, two fabs in China, two in the United States and one in Japan ².

Variants and trade-offs

Pure-play foundries

TSMC and UMC build only for others. Chips at 7 nm and below, meaning the newest processes, were 77 percent of TSMC's wafer revenue in the second quarter of 2026, split 33 percent at 5 nm, 30 at 3 nm, 11 at 7 nm and 3 at 2 nm, on revenue of $40.20 billion at a 67.7 percent gross margin ⁶.

Integrated device makers turned foundry

Intel and Samsung design and sell their own chips and rent out capacity too. Renting out capacity is harder for them, because customers dislike handing designs to a competitor and the company's own products take the best capacity. Intel Foundry reported $5.8 billion of segment revenue in the second quarter of 2026 and an operating loss of $2.089 billion ⁷. Only $293 million of that revenue came from outside customers, and Intel says substantially all of its foundry business still makes Intel's own products ⁸.

National champions

SMIC, Hua Hong and Rapidus have government backing. SMIC's revenue rose 16.2 percent to $9.327 billion in 2025 at 93.5 percent utilization, on monthly capacity above a million wafers counted in the smaller 8-inch size, and a 21 percent gross margin ⁹. SMIC cannot buy an EUV scanner, yet it makes 7 nm-class chips on its N+2 and N+3 processes by printing the tightest layers in several passes on older deep-ultraviolet scanners ¹⁰. CSET reported in June 2024 that Huawei's Ascend 910B AI chip is believed to be made on N+2, and that SMIC's limited 7 nm capacity forced Huawei to choose between its most advanced phone chips and its AI chips ¹¹. SemiAnalysis judged in April 2025 that most 910B and 910C chips were in fact made on TSMC's 7 nm process, from wafers Huawei bought through another company ¹². Rapidus raised 267.6 billion yen from the Japanese government and 32 companies in February 2026 to carry it to 2 nm mass production by 2027 ¹³.

Mature-node capacity

Most wafers come off older lines, which make power devices, analog chips and microcontrollers and compete on price. In January 2025 the industry association SEMI forecast that foundry capacity at all nodes would rise from 11.3 million wafers a month in 2024 to a record 12.6 million in 2025, counted in the 8-inch size ¹⁴. Its June 2024 forecast had credited much of that growth to Intel's new foundry business and China's expansion ¹⁵. In July 2025 Intel scaled back its own fab plans, saying it would no longer go ahead with planned projects in Germany and Poland and would slow construction in Ohio ¹⁶.

Capacity and cost

TSMC added $100 billion in March 2025 to the $65 billion already committed in Phoenix, for three more fabs, two packaging plants and an R&D center ¹⁷. In July 2026 it added another $100 billion for four more fabs at 2 nm or below, taking its total investment in Arizona to $265 billion across 12 facilities ¹⁸. All of TSMC's gigafabs are still in Taiwan ².

Some customers pay TSMC in advance to hold capacity at its fabs, and these deposits stood at NT$189.9 billion at the end of 2025, down from NT$291.1 billion a year earlier ¹⁹. In 2025 the four largest AI chip designers used around 90 percent of the world's CoWoS packaging capacity and HBM memory supply, against only 12 percent of advanced logic production ²⁰. See Advanced packaging.

Who makes it

Intel is now partly state-owned. In August 2025 Washington bought 433.3 million newly issued Intel shares at $20.47, or $8.9 billion, for a 9.9 percent stake, paid out of $5.7 billion of unpaid CHIPS Act grants and $3.2 billion from the Secure Enclave program. The stake is passive, with no board seat, and the government agreed to vote with Intel's board on matters that need shareholder approval, with limited exceptions. The deal also came with a five-year warrant to buy a further 5 percent of Intel at $20 a share, which Washington can exercise only if Intel's ownership of its foundry business falls below 51 percent ²¹.

Intel's technical position improved in 2026. It reached high-volume manufacturing on part of Panther Lake using ASML's High-NA extreme ultraviolet scanners, and put 18A-P into risk production, the trial runs a process goes through before it is signed off ⁷.

Samsung broke ground in Taylor, Texas, in 2022 on a plant with an initial minimum investment of $17 billion, $6 billion of buildings and $11 billion of equipment ²². In December 2024 the Commerce Department awarded Samsung up to $4.745 billion of CHIPS Act funding to support more than $37 billion of planned investment in Central Texas, covering two new leading-edge logic fabs and a research fab in Taylor and an expansion of its existing plant in Austin ²³.

The chokepoint

In June 2024 SEMI forecast China at 10.1 million wafers a month in 2025, the most of any region, against Taiwan's 5.8 million out of a world total of 33.7 million ¹⁵. In the third-quarter 2026 update of its World Fab Forecast, SEMI projected that China would keep the largest installed capacity in 2026 and 2027 ²⁴. Little of China's is advanced; in 2022 South Korea and Taiwan held almost all of the world's logic capacity below 10 nm ²⁵. The United States had almost no capacity below 10 nm in 2022, and in May 2024 SIA and BCG projected it would hold 28 percent of it by 2032, while new fab investment worldwide reaches around $2.3 trillion from 2024 to 2032 ²⁵.

Three risks meet on one island:

• Seismic. Taiwan sits on an active plate boundary, and after an earthquake in January 2025 TSMC had to scrap a number of wafers in process ²⁶.
• Power. A gigafab is a large industrial load on a small island grid.
• Political. Taiwan held 69 percent of the world's logic capacity below 10 nm in 2022 ²⁵. In December 2025 SemiAnalysis put Taiwan's share of the world's advanced-node capacity, a term it did not tie to a node size, at over 90 percent, so a blockade or conflict would cut most of that output off from the world market at once ²⁷. See Geopolitics.

Diversification is slow, and TSMC has yet to build a gigafab anywhere but Taiwan ².

Key evaluation criteria

• Leading-edge share. The share of revenue from the newest processes, 77 percent of TSMC's wafer revenue at 7 nm and below in the second quarter of 2026 ⁶.
• Yield at ramp. How many good chips a new process gives in its first year, which separates a profitable node from a subsidized one.
• Ten-year cost of ownership. $35 to $43 billion for a new 2 nm-class fab finished in 2026, in BCG's 2023 estimate, and rising ⁴.
• Utilization. How full the lines run. SMIC's lines ran 93.5 percent full in 2025, at a 21 percent gross margin ⁹.
• Customer concentration. A foundry owned by a chipmaker competes with its own customers, which caps who will trust it with a flagship design.
• Geographic exposure. How much of a buyer's supply sits on one island, one grid, one fault system.

An AI accelerator is a machine for moving numbers past arithmetic units, and arithmetic got cheap faster than the moving did. The US export control office notes that a processor cannot reach its full capabilities unless its memory capacity and bandwidth rise with its speed ¹.

How it works

Each layer in the cube is a DRAM chip, ground thin and bonded to the one below through microbumps, tiny metal bumps, and the whole stack sits on a base die that manages it. The copper-filled holes are TSVs, through-silicon vias, and they let a signal reach any layer without a wire around the outside.

An HBM3E cube talks to the processor over 1,024 wires at once, a 1,024-bit interface, sixteen times wider than a standard DDR5 memory module, the memory stick in a PC ². HBM4 doubles that to 2,048 wires ³. Ordinary memory cannot be made that wide, because the pins would not fit on a circuit board. The stack can, since its wires run down through the TSVs and across a silicon interposer to the processor beside it, with no board in the way ².

Inside a memory stack

1. 01Base chip
2. 02Thin
3. 03Stack
4. 04Height
5. 05Width

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A memory stack sits beside the GPU on a shared silicon base. It starts with a base chip, which controls the memory chips above it.

1. Base chip. A memory stack sits beside the GPU on a shared silicon base. It starts with a base chip, which controls the memory chips above it.
2. Thin. Each memory chip is ground to about 30 micrometers, thinner than a human hair.
3. Stack. Twelve chips are joined by dots of solder, and copper-filled holes run straight down through all of them.
4. Height. The stack has to fit under the cooling plate. Twelve chips reach 0.72 mm, the old limit. HBM4 raised the limit to 775 micrometers and fits up to sixteen chips.
5. Width. An HBM3E stack talks to the processor over 1,024 wires at once, sixteen times as many as a PC memory module. HBM4 doubles that to 2,048.

Simplified cross-section. Heights follow the published limits and are drawn to one vertical scale; widths are not to scale.

Answering a prompt is what the width is for. Training reuses each stored number across a huge multiplication, so a chip can fetch little and compute a lot. To generate one word of an answer, the chip reads the whole model from memory, and the whole record of the conversation so far, does a little arithmetic, and waits for the next read. That record grows with the length of the conversation and the number of users served at once. So memory size and speed usually set how many people one chip can serve.

Variants and trade-offs

HBM3E

Micron ships the high-volume parts, 24 GB with eight chips stacked and 36 GB with twelve ⁴. SK hynix's January 2026 market outlook says major research and brokerage analysts expect HBM3E to be about two thirds of all HBM shipments in 2026 ⁵.

HBM4

The standards body JEDEC published JESD270-4 in April 2025, setting the 2,048-bit interface and 2 TB/s per stack at 8 Gb/s per pin ³. SK hynix says it was first to complete HBM4 development, in September 2025, at over 10 Gb/s per pin ⁶. Samsung says it began mass production and shipped the first commercial HBM4 in February 2026, at 11.7 Gb/s per pin, with a 4 nm logic base die ⁷. Micron's parts run above 11 Gb/s for more than 2.8 TB/s per stack ⁸.

The chip at the bottom of the stack is a base die, and SK hynix, which made its own base dies up to HBM3E, chose TSMC's advanced logic process for the HBM4 base die so it can hold more functions ⁹. That gives TSMC a role inside a product it does not make.

How a stack is built

• Drill and thin. Etch vertical holes, the through-silicon vias, into a memory wafer, fill them with copper, then grind the wafer from behind until the copper comes through.
• Stack and join. The chips are joined by thermocompression bonding, which connects them through metal bumps under heat and pressure and comes in several forms ¹¹. SK hynix uses Advanced MR-MUF, which stacks the chips, injects a liquid protective material between them and hardens it, and the company says the process controls warping and dissipates heat well ⁶. Samsung said in February 2024 that its twelve-high HBM3E uses TC-NCF, thermocompression with a thin non-conductive film between the chips, which it expected to help limit warping as chips get thinner ¹².
• Stay under the height limit. HBM4 raised the package specification height of a finished cube from 720 micrometers to 775, still under a millimeter ¹¹.

Hybrid bonding is the next step and it is not ready. Pressing copper pad straight onto copper pad, with no solder and no filler, would cut the spacing between connections from about 20 micrometers to under 1, but a tech note on SK hynix's newsroom says full-scale adoption in HBM is most likely at HBM4E or HBM5, where stacks are projected to pass twenty layers ¹¹.

Who makes it

Ordinary computer memory, DRAM, is a three-firm oligopoly, and HBM is the same three firms reordered: SK hynix, Samsung and Micron ¹³. Nobody else has both leading-edge DRAM and a stacking line inside one company.

SK hynix was the first company to mass-produce several generations of HBM, including HBM3 and HBM3E ¹³. UBS, as quoted in SK hynix's January 2026 market outlook, expected SK hynix to take about 70 percent of the HBM4 market for Nvidia's Rubin platform in 2026 ⁵. Samsung says it shipped the first commercial HBM4 in February 2026 ⁷. SK hynix broke ground in August 2026 on an advanced packaging plant in West Lafayette, Indiana, an investment of over $4 billion ¹⁴. Micron is modernizing its DRAM and HBM production capacity in Taiwan and has broken ground on an HBM advanced packaging plant in Singapore to expand its packaging capacity from 2027 ¹⁵.

The split is on the record because SK hynix registered shares in the United States: of 2025 HBM revenue, SK hynix took 63.2 percent, Samsung 19.3 and Micron 17.4 ¹³. The filing credits the research firm IDC. These shares move fast, and in 2024 the same three stood at 56.4, 37.8 and 5.8 percent ¹³. In the first quarter of 2026 they stood at 56.4, 20.5 and 23.1 percent ¹³.

Bank of America, in an estimate SK hynix quoted in January 2026, put the 2026 HBM market at $54.6 billion, up 58 percent on 2025 ⁵. SK hynix says HBM requires greater wafer input than traditional DRAM ¹³. It also says the industry-wide reallocation of production capacity to HBM has left traditional DRAM, the kind used in PCs and phones, undersupplied, which helped drive a significant price recovery in that market from the third quarter of 2025 ¹³.

The chokepoint

Every leading accelerator made outside China depends on Korean or American HBM. Nvidia's GB300 NVL72 carries 20 TB of HBM3E at up to 576 TB/s ¹⁶, Rubin up to 288 GB of HBM4 per GPU at up to 22 TB/s ¹⁷, and AMD's MI355X 288 GB of HBM3E at 8 TB/s ¹⁸.

The Bureau of Industry and Security rule of 5 December 2024, at 89 FR 96790, added an export classification, ECCN 3A090.c, for "High bandwidth memory (HBM) having a 'memory bandwidth density' greater than 2 gigabytes per second per square millimeter". Its technical note defines that density as the memory bandwidth in gigabytes per second divided by the area of the package or stack in square millimeters. The rule also reaches stacks made outside the United States, through a foreign direct product rule that catches goods made abroad with American technology ¹. BIS stated in the rule that all HBM stacks then in production exceeded that threshold ¹. Under 15 CFR 742.6(b)(10)(ii) BIS reviews applications for 3A090.c to Macau or a Country Group D:5 destination such as China with a presumption of approval when neither the buyer nor its ultimate parent is headquartered in one of those places, and with a presumption of denial otherwise ¹⁹.

Two provisions narrow the control. License Exception HBM, at 15 CFR 740.25, lets an exporter headquartered in the United States or a Country Group A:5 ally ship HBM below 3.3 GB per second per square millimeter without a license, if the designer of the co-packaged chip buys it directly and it goes straight to the packaging site ²⁰. The rule also excludes co-packaged chips that combine HBM and logic and whose main function is processing, which other chip controls may cover instead ¹. CSIS said in December 2024 that the rules still allowed HBM2 to go to China with end-use and end-user restrictions, and that Nvidia's H20, whose HBM3 is packaged with the processor, was then still exportable under the accelerator thresholds ²¹.

In December 2024 CSIS called China's strongest DRAM maker, CXMT, one of only two Chinese firms with a credible path to producing advanced HBM ²¹. The Institute for Progress reported in October 2025 that CXMT was planning to produce HBM3 in 2026 ²². Huawei said in September 2025 that its Ascend 950 chips would use two HBM designs of its own, HiBL 1.0 and HiZQ 2.0, and that the 950DT, due in the fourth quarter of 2026, would carry 144 GB of HiZQ 2.0 at 4 TB/s ²³. The announcement did not say who would manufacture the memory ²³. SK hynix says HBM requires advanced production processes such as TSV packaging and compliance with the rigorous testing and approval processes its customers set ¹³.

Key evaluation criteria

• Bandwidth per stack sets how fast a chip can serve answers: over 1.2 TB/s on HBM3E, over 2 TB/s on HBM4 ¹⁰.
• Capacity per stack decides how large a model fits on one accelerator, up to 64 GB with sixteen chips stacked in the JEDEC HBM4 standard ³. Samsung said in February 2026 that its twelve-high HBM4 comes in 24 to 36 GB and that sixteen-high parts would take it to 48 GB ⁷.
• Stack height, 775 micrometers in the HBM4 package specification, caps how many layers fit in a stack ¹¹.
• Stack yield matters because a chip that fails after stacking can scrap the whole cube. Micron sends only dies that pass testing on to assembly and tests the finished cube again ⁸.
• Thermal path gets harder with every layer, and heat dissipation becomes a major challenge at 16 to 20 layers as heat builds up in the stack ¹¹.
• Qualification means passing each customer's tests, and SK hynix credits its experience with complex qualification processes for its standing as a trusted HBM supplier ¹³.

A lithography scanner prints a rectangle 26 mm by 33 mm, or 858 mm2, in one exposure ¹. Every AI accelerator worth buying is bigger than that. Packaging is the stage that lets an accelerator be larger than that rectangle, and it decides how much larger.

How it works

High bandwidth memory gives a second reason for the interposer. An HBM4 stack connects through 2,048 data signals, packed too tightly for a standard resin base board, so the memory sits beside the logic on that shared carrier, the interposer ². Even Nvidia's H100, whose single logic die is 814 mm2 and fits inside one exposure, carries five HBM stacks ³. Epoch AI counts CoWoS packaging among the three inputs the H100 needs, along with its logic die and its HBM ⁴.

The parts of an AI accelerator

1. 01Package base
2. 02Silicon base
3. 03Logic chips
4. 04Memory
5. 05One package

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An AI chip is built from several parts. First comes the package base, a layered board that connects everything to the circuit board below.

1. Package base. An AI chip is built from several parts. First comes the package base, a layered board that connects everything to the circuit board below.
2. Silicon base. On it sits a thin slab of silicon, called an interposer. Its fine wiring joins everything placed on top.
3. Logic chips. Two logic chips go in the middle. They do the calculating, and each is as large as a chipmaking machine can print.
4. Memory. Eight stacks of memory go beside them, a few millimeters away. They hold the AI model’s weights and the record of each conversation so far.
5. One package. Together they make one AI accelerator. Nearly every one is put together by TSMC, in Taiwan.

Simplified view of a two-die, eight-stack accelerator. Footprints follow the sizes in this chapter and chapter 10; heights are exaggerated so each layer shows.

The name CoWoS says the order: chip onto wafer, then wafer onto substrate. For CoWoS-S, TSMC makes a thin silicon wafer carrying wiring and vertical copper vias, metal-filled holes that join one layer of wiring to the next, but no transistors. It bonds the logic dies and memory stacks face down onto that wafer with microbumps, dots of solder 30 to 40 microns apart, about a third of a hair's width, each dot one electrical joint. Then it cuts the interposer out of the wafer, attaches it to the resin substrate, and the substrate goes onto its board.

Each of those packaging steps is ordinary on its own. But one cracked joint scraps a package holding eight qualified HBM stacks and two large, expensive logic dies.

Variants and trade-offs

2.5D: silicon, RDL and bridges

TSMC has run CoWoS in volume since 2012 ⁵. CoWoS-S wires most finely, but its interposer is one unbroken piece of silicon whose yield falls as the area grows. CoWoS-L replaces that slab with an interposer of redistribution wiring and small embedded silicon bridges where the wiring is densest ⁶. Intel's EMIB buries the same bridge idea in the resin substrate, and SemiAnalysis reported in March 2026 that Trainium and TPU were adopting it to different degrees ⁷.

Blackwell was the first high-volume design on CoWoS-L, and packaging issues at TSMC and in Nvidia's design limited its supply ⁸. The bridges carrying the 10 TB/s link between the two compute dies need very high placement accuracy, and the different expansion rates of the dies, bridges, interposer and substrate caused warpage ⁸.

3D: SoIC and Foveros

TSMC's SoIC and Intel's Foveros bond dies face to face, copper pad to copper pad with no solder, packing the connections far closer than microbumps allow. TSMC put 3 nm SoIC into volume production in 2025 ⁶. An A14-on-A14 version due in 2029 will carry 1.8 times the die-to-die connection density of the 2 nm version ⁹. Heat decides the layout: the bottom die overheats and the top is hard to power, so 3D designs often put cache underneath and compute on top.

The same bonding brings optics into the package. TSMC's COUPE uses SoIC to join a silicon photonics chip, which sends data as light, to its electrical control chip ⁶. TSMC said in April 2026 that COUPE on substrate would begin production in 2026, and that placing this optical engine inside the package gives twice the power efficiency of a pluggable version on the circuit board ⁹.

Two ways off the silicon interposer

Panel-level packaging swaps the round wafer for a rectangular panel and wastes far less area; see Test and assembly. JEDEC published SPHBM4 on 13 July 2026. It puts HBM4 memory on a base chip carrying 512 data signals instead of 2,048, which spaces the connections widely enough to mount the stack on a standard resin substrate, off the silicon interposer altogether ².

Capacity

TSMC does not publicly disclose its CoWoS capacity ⁴. Industry estimates from SemiWiki and TrendForce, compiled by Epoch AI, put it at about 65,000 to 75,000 wafers a month at the end of 2025, up from 35,000 to 40,000 a year earlier ⁴. At its 2024 symposium TSMC said capacity would grow at a 60 percent compound annual rate over the next few years, but when asked about that rate on the July 2024 earnings call, C.C. Wei said only that he would keep adding capacity wherever he could and could not yet balance supply and demand ¹⁰.

In October 2025 Wei would still say only that TSMC was working to increase capacity in 2026 and would probably give the real number in 2026, and that front-end and back-end capacity were both, in his words, very tight ¹¹.

Epoch AI weighs each designer's component use against world supply and puts Nvidia at 60.3 percent of all CoWoS in 2025, with a 90 percent confidence interval of 56.5 to 64.3; Google took 13.5, AMD 8.4 and Amazon 7.4 ⁴. Those four consumed around 90 percent of global CoWoS capacity and HBM supply, with HBM measured by value, while consuming only 12 percent of advanced logic die production ⁴.

In March 2026, one analyst firm, SemiAnalysis, judged that front-end capacity had become the dominant bottleneck and CoWoS constraints were easing, and that TSMC was planning CoWoS capacity around its N3 limits because added packaging capacity is of no use without front-end wafers to fill it ⁷.

TSMC gave a different account four months later. On the July 2026 earnings call, Wei said its packaging capacity was so tight that it limited customers' growth, and that back-end capacity was still in shortage ¹². Asked about Intel's EMIB-T, he said he welcomed the extra flexibility and hoped it would take some of the load off TSMC ¹².

Who makes it

The word packaging covers three kinds of firm. TSMC, which makes chips for others, and Intel, which makes its own, package chips in their own back-end fabs, and outsourced assembly and test firms do the rest. Intel opened Fab 9 in Rio Rancho, New Mexico, in January 2024 to make its Foveros 3D packages in volume, and called it the only US factory producing the most advanced packaging at scale ¹³. ASE Technology Holding, the leading provider of assembly and test services, billed NT$645.4 billion in 2025, about 40 percent of it from electronics manufacturing services ¹⁴. Its assembly, test and materials business brought in NT$389.2 billion, up from NT$325.9 billion in 2024 ¹⁴. Amkor, the world's largest US-headquartered one, billed $6.71 billion ¹⁵.

The tools are a narrower chokepoint than the assembly houses.

• Thermocompression bonding. Pressing dies together under heat and force. ASMPT's advanced packaging revenue reached $532.1 million in 2025, with thermocompression bonder revenue up about 146 percent; it targets 35 to 40 percent of a market it puts at $1.6 billion in 2028 ¹⁶.
• Hybrid bonding. Solder disappears and copper pads meet directly. Applied Materials co-developed its Kinex hybrid bonding system with Besi, which Applied calls the industry leader in hybrid bonding ¹⁷.
• Grinding and dicing. Disco held 87 percent of the $1.9 billion world market for dicing tools in 2025, a category that covers the grinders that thin wafers and the saws that cut them into chips, by CSET's count from TechInsights data; see Test and assembly ¹⁸.

TSMC's Arizona commitment reached $265 billion in July 2026 and covers two advanced packaging plants alongside 10 fabs ¹⁹. Amkor started building a $7 billion campus in Peoria in October 2025 and expects production from early 2028 ²⁰. The Commerce Department awarded Amkor up to $407 million in CHIPS Act funding for the site in December 2024 ²¹. In October 2025 Wei said a large outsourced packaging partner already breaking ground in Arizona was on an earlier schedule than TSMC's own two packaging fabs there ¹¹.

The chokepoint

JCET, a leading Chinese assembler, billed a record RMB 38.87 billion in 2025, up 8.1 percent ²³. Between 2019 and 2024, Chinese firms gained 5 percentage points of share in test tools and 4 points in fabrication tools built for advanced packaging, but lost share in bonding and other conventional assembly and packaging tools, the category where CSET counts hybrid and thermocompression bonders ²². Within those advanced packaging fabrication tools, China gained 10 points in etch and clean tools and 3 points in deposition tools, and lost 2 points each in lithography and CMP tools ²². In 2024 China held 7 percent of advanced packaging fabrication tools, against 65 percent for the United States and 15 percent for Japan ²². Four of the top ten outsourced assembly and test firms by 2024 revenue are headquartered in China ²². JCET says its XDFOI platform has entered high-volume manufacturing with redistribution-layer interposer, silicon interposer and silicon bridge options ²⁴.

Each generation on TSMC's roadmap needs a larger interposer.

• 2028. A 14-reticle interposer carrying about ten large compute dies and 20 HBM stacks, roughly 12,000 mm2 of interposer, about the area of a compact disc ⁹.
• 2029. More than 14 reticles, and a 40-reticle System-on-Wafer beside it ⁹.

Key evaluation criteria

• Interposer area is the limit on how much logic and memory fit, now 5.5x reticle on CoWoS-L ⁹.
• Package yield decides whether a generation ships on time, and nobody publishes it.
• Warpage control covers the expansion mismatch between die, bridge, interposer and substrate that caused warpage in Blackwell, the first high-volume CoWoS-L design ⁸.
• HBM stacks supported is about 20 on the 14-reticle package due in 2028 ⁹.
• Bonder throughput depends on the toolmakers, and ASMPT alone targets 35 to 40 percent of the thermocompression bonding market ¹⁶.
• Substrate size limits everything above it. A 14-reticle interposer needs a resin substrate that will not warp under it, which pushes ABF build-up film to its limits; see Substrates and PCBs.

On TSMC's July 2026 earnings call, chief executive C.C. Wei said packaging capacity is now so tight that it limits customers' growth ¹. The silicon interposer wires chips together inside a package. Past its edge the wiring turns to epoxy and glass: a build-up substrate, a printed circuit board of thirty layers, then a rack.

How it works

How a substrate fans out

1. 01The package
2. 02Tight to wide
3. 03Layer by layer
4. 04Connected

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An AI chip is more than the chip itself. It sits in a package: the chips on a silicon base, and under them the substrate, which connects everything to the circuit board.

1. The package. An AI chip is more than the chip itself. It sits in a package: the chips on a silicon base, and under them the substrate, which connects everything to the circuit board.
2. Tight to wide. The connections on top are packed tight. The circuit board below is wired in millimeters. The substrate has to join the two.
3. Layer by layer. The substrate does it in layers, built outward from a stiff core. Each layer carries the copper a little further out.
4. Connected. Stacked together, the layers fan the tight grid out to the board’s wide one. An AI chip needs about 18 layers, against six for a PC, and every layer is another chance for a flaw, which is what makes these substrates hard to build.

Simplified. Eight layers are drawn, and every thickness is exaggerated.

The substrate maker drills the core and plates it with copper before the build-up starts. Each cycle then presses on a film of epoxy, burns holes through it with a laser to connect the layers, and adds copper wiring on top ². Each film is about 10 micrometers thick, and a human hair is about 80 micrometers across ³.

Silicon and epoxy swell at different rates when heated, so the larger the package, the more it warps. Ajinomoto counts 22 layers of its film in a 2026 AI package substrate about 100 mm square, against 18 on a high-performance computing substrate about 70 mm square around 2023, and six when PCs first adopted it in 1999 ². Nitto Boseki says its low-expansion T-glass cloth has been highly evaluated as an effective solution to that warping, and its adoption in substrates has increased significantly ⁴.

Variants and trade-offs

BT substrates

Bismaleimide-triazine laminate, or BT, is the other main family. Mitsubishi Gas Chemical, which makes BT materials, says they go mostly into thin packages for smartphone processors, radio modules and memory ⁵. The company also lists flip-chip substrates for computer CPUs and GPUs among BT's uses, where its laminate forms the core between layers of build-up film ⁵. In an October 2024 investor presentation, it estimated that its BT resins held about 40 percent of the substrate materials market ⁵.

ABF build-up substrates

Ajinomoto Build-up Film, or ABF, is the insulating film between the layers of package substrates for logic chips, used in PCs, network equipment, servers and AI equipment ². Ajinomoto first developed it in 1999, and says major chipmakers have used it as the de facto standard ever since ⁶. Asked on the company's own site whether its share was nearer 30 or 50 percent, the electronic materials division answered: "More like 95 percent market share", and said practically all high-performance computers and servers rely on it ³. In June 2026 Ajinomoto told investors that the film has held a share of over 95 percent since its launch ².

Glass core substrates

A glass core in place of resin expands less with heat and stays flatter, which is why chipmakers and substrate makers are both trying it ⁷.

• Absolics, a subsidiary of Korea's SKC, has a final Commerce Department award of up to $75 million for a 120,000-square-foot glass substrate plant in Covington, Georgia, and as of October 2026 NIST's project page expected first deliveries to customers in 2025 and production capacity to come online in 2027 ⁸.
• Intel announced glass substrates in September 2023 for the latter part of this decade ⁹.
• Samsung Electro-Mechanics signed a joint venture agreement with Sumitomo Chemical's subsidiary Dongwoo Fine-Chem in July 2026 to make glass core substrates, with a supply system planned by the second half of fiscal 2027 ¹⁰.

All three timelines reach into the later years of this decade.

The materials underneath

Ajinomoto's film is a small line in a food company's accounts and a chokepoint for high-end chip packages. The Healthcare and Others segment that carries electronic materials lifted business profit 45.1 percent to JPY 66.2 billion in the year to March 2026, which Ajinomoto attributes mainly to higher electronic materials revenue and higher profit in Bio-Pharma Services & Ingredients ¹¹. Ajinomoto has set an investment budget of JPY 25 billion between 2023 and 2030 to expand production, and says there are no concerns about its current supply chain overall ². In May 2026 it announced the acquisition of land in Gifu Prefecture for a third production site, scheduled to start operating in 2032 to meet demand after 2030 ².

The core one layer down also has a dominant supplier. Nitto Boseki's T-glass is stiff and expands little when heated, and the company calls it essential for making high-density package substrates ⁴. Laminate makers such as Mitsubishi Gas Chemical coat the glass cloth with resin and press it with copper foil into the core laminate that substrate makers build on ⁵. Nitto Boseki claims an overwhelming advantage in quality and capacity for low-expansion glass, says market demand seems to have risen about two to three times since its fiscal 2024 to 2027 plan was set, and planned about JPY 80 billion of capital spending over those four years ⁴. In August 2025 it decided to expand glass fiber cloth production at its Fukushima Enterprise Center, with production scheduled to begin in the fourth quarter of its fiscal 2026 ⁴. Apple and Qualcomm are among the customers worried about Japanese glass cloth supply ¹².

Chinese firms are entering this layer, and Nitto Boseki says Chinese and Taiwanese companies are aggressively catching up with it in the special glass sector ⁴. At stake is a chip materials market Nikkei sizes at $73 billion ¹³.

Who makes it

The plants that build substrates for other firms are an Asian oligopoly. The White House's 2021 hundred-day supply chain review recorded build-up substrate among the materials commenters called vulnerable, and named key substrate makers including Ibiden, Nanya, Shinko, Samsung, Unimicron, Shennan Circuits, Zhuhai Yueya and AKM. None of the eight is American ¹⁴. A May 2024 report by the Semiconductor Industry Association and Boston Consulting Group counted the major vendors of package substrates by headquarters and found two in Japan, two in Taiwan, one in mainland China and none in the United States ¹⁵. TTM Technologies, an American circuit board maker, says it also offers IC substrates ¹⁶.

• Ibiden will invest about JPY 500 billion from fiscal 2026 to fiscal 2028, starting with about JPY 220 billion, mainly at its Gama plant, and planned mass production from fiscal 2027 ¹⁷. In May 2026 management said it typically takes close to 100 percent of a new generation of interposer-type substrates at launch, and that this share may decline by 20 to 30 percent after about three to six months ¹⁸. On silicon-bridge substrates, it said, wiring the underside is hard enough that it expects to keep its technical lead at least through fiscal 2030 ¹⁸.
• Unimicron took NT$42.9 billion of sales in the second quarter of 2026, 52 percent of it build-up substrates and 61 percent of it AI data center work ¹⁹.
• Samsung Electro-Mechanics grew package solution sales 37 percent year on year to KRW 771.6 billion in the second quarter of 2026, on substrates for AI accelerators, server processors and cars ²⁰.

A company owned mainly by funds of JIC Capital, a subsidiary of Japan Investment Corporation, launched a tender offer for Shinko's other shares in February 2025 as part of a deal to take it private, and Fujitsu agreed to sell its 50.02 percent stake back to Shinko ²¹. The tender offer succeeded in March 2025 ²². In September 2026 Shinko agreed to buy a plant in Mobara, Chiba Prefecture, from Japan Display, a display maker, and said it would make the site a new core plant for advanced chip packages while also expanding capacity at its plants in Nagano ²³. Production there is scheduled to start in fiscal 2028 ²³.

The boards under the GPU

TTM Technologies says it regularly builds printed circuit boards of more than 30 layers and can go past 70 ¹⁶. Those layers carry power to the GPUs and route fast signals between them, so how much signal the laminate absorbs becomes a main design constraint. Nitto Boseki also makes NE-glass, a low-dielectric glass cloth that absorbs less signal, used in switches and routers in data centers ⁴.

Data center computing was 24 percent of TTM's $2.91 billion of fiscal 2025 revenue, against 14 percent two years earlier ¹⁶. It says its circuit board competitors are mostly based in China and Taiwan ¹⁶. In its annual report for 2025, TTM said it was building a plant in Syracuse, New York, to make ultra-high-density circuit boards for national security needs, with volume production expected in the second half of 2026 ¹⁶. Thailand aims to be the biggest circuit board hub outside China as makers race to diversify production ²⁴.

The chokepoint

Money can expand an oligopoly of substrate plants, and it is being spent. The weakest points are one layer down, where one Japanese company dominates the film and another dominates the low-expansion glass cloth in the core. Both are adding capacity on plans that run for years.

Packages lose flatness as they grow. TSMC has told investors that its CoWoS packaging roadmap goes beyond 14 times the area a lithography machine can print in one shot ¹. Bigger bodies mean more warping, more layers, more holes that can break the circuit, and lower yield on a part that is already expensive before a die touches it.

Key evaluation criteria

• Layer count sets how much current and how many signals the substrate can carry. Each added layer is another chance to lose the part.
• Body size drives everything else. Once a body is much larger than the dies it carries, warping and handling take over from the wiring in deciding what can be built.
• Coefficient of thermal expansion, how much a material swells when heated, must be close enough to silicon that the package survives repeated heating and cooling, which is what T-glass provides and why its supply matters.
• Dielectric properties, how much signal the core laminate absorbs, set the speeds the substrate and the board underneath can run.
• Qualification time protects the incumbents. A second supplier's film or laminate has to be approved by each substrate maker and chip customer before it can be used.

Turning silicon into a finished, packaged chip takes 1,000 to 1,500 steps, depending on how complex the chip is, the Semiconductor Industry Association estimated in 2025 ¹. Advantest's investor guide of July 2026 counts test as the only step that puts electrical signals through the chip ². Every stage so far makes dies; the back end of the industry, assembly and test, decides which of them are allowed into a package.

How it works

How a chip is tested

1. 01The wafer
2. 02Needles
3. 03Questions and answers
4. 04Chip by chip
5. 05Into the package

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Every stage so far makes chips. Before any of them can be sold, a machine tests each one, starting while the chips are still on the wafer.

1. The wafer. Every stage so far makes chips. Before any of them can be sold, a machine tests each one, starting while the chips are still on the wafer.
2. Needles. A probe card lowers thousands of needles onto one chip. They press onto small metal pads on its surface.
3. Questions and answers. Through the needles, the tester sends signals into the chip and reads what comes back. It checks every answer.
4. Chip by chip. The tester steps from chip to chip across the wafer. It marks any chip that answers wrong, and that chip goes no further.
5. Into the package. Only chips that pass go on to be packaged. A modern accelerator glues together a dozen expensive pieces, and one bad piece throws away all of them, so each piece is tested before it goes in.

Simplified. Nine needles stand for thousands, and the failed chips are placed for illustration and show no real yield. The package follows chapter 11: two logic chips and eight memory stacks on a silicon base and a package base.

Each round of test catches failures the round before it cannot see.

• Wafer sort. Thousands of needles land on each die while it is still on the wafer, a tester drives patterns in and checks the answers, and the failures go no further.
• Burn-in. Run the part hot and at raised voltage for minutes to days, on the wafer or in the package, so anything that would fail early fails in the factory ³.
• Final test. The tester runs the packaged part again, because packaging adds failures of its own.
• System-level test. The finished part sits in a socket and runs something close to a real workload, because some failures appear only when everything runs at once.

Proving a die good before it is packaged matters more as packages hold more valuable parts ⁴. Aehr's wafer-level burn-in systems look for early-life and hidden failures before dies are cut from the wafer, which lowers the risk of committing high-bandwidth memory and an expensive substrate to a processor that may later fail ⁴. Aehr's lead AI customer is shifting burn-in for its AI accelerators from the finished system to the wafer ⁵. The FOX-XP systems that customer ordered from Aehr in August 2026 each burn in nine 300 mm wafers at a time ⁴.

Variants and trade-offs

Wafer sort and known-good die

The probe card that holds those needles is the hard part. FormFactor says the high-frequency capability of its probe cards lets it compete favorably in testing high-bandwidth memory, a stack of eight, twelve or even sixteen memory dies ⁶. For a large logic die every needle must sit in the same plane, survive repeated touchdowns without drifting, and do it hot. Cards are custom to the device, so each new part means a new card and a new qualification.

Final test, burn-in and system-level test

The economics get worse as packages grow. TSMC has told investors that its CoWoS packaging roadmap runs beyond 14 times the area a lithography machine can print in one shot ⁷. Every added die is another chance to lose the whole assembly, along with its memory and substrate ⁴. ASE ran 6,797 testers in the second quarter of 2025 and 8,348 a year later ⁸.

Who makes it

Advantest puts its own share at about 65 percent of an estimated $9.0 billion tester market in 2025 ⁹. Its share of system-on-chip (SoC) testers, the machines that test processors and other non-memory chips, rose about ten points in a year to 66 percent, and it held about 60 percent of memory test ⁹. Teradyne, its main rival, took $2.52 billion of semiconductor test revenue in 2025, service included, of which $1.89 billion came from SoC testers and $505 million from memory testers ¹⁰. Teradyne as a whole grew 13 percent to $3.19 billion for 2025, with fourth-quarter revenue up 44 percent on AI demand ¹¹.