Design is the only stage of the supply chain that happens entirely in software, and the US government has already restricted it by letter. In late May 2025 the government required a license to sell chip design software to anyone in China². Cadence cut off its Chinese customers until the government lifted the requirement on 2 July².

How it works

How a chip is designed

1. 01A blueprint
2. 02One tick
3. 03Too far
4. 04Placed closer
5. 05Checked

Paused

Making a chip starts with design, which turns an idea into a complete blueprint. The blueprint fixes where each of the chip’s billions of switches sits and how each one is wired to the others.

1. A blueprint. Making a chip starts with design, which turns an idea into a complete blueprint. The blueprint fixes where each of the chip’s billions of switches sits and how each one is wired to the others.
2. One tick. The chip works in ticks, each less than a billionth of a second. On every tick a signal leaves a register, a small store that holds one number, and it has to cross its wire to the next register before the next tick.
3. Too far. If the next register sits far away, the wire is long. The signal is still on its way when the next tick comes, so it arrives too late.
4. Placed closer. Design software from three companies, Synopsys, Cadence and Siemens, places the parts and wires them together. Here it moves the register closer, and the signal arrives in time.
5. Checked. The software checks that every signal arrives in time and that every shape can be printed, and a chip factory accepts only designs that pass the printing checks. The factory then prints the blueprint onto silicon through stencils, and changing it after that costs new stencils and a few months.

Simplified. Not to scale. The floorplan follows a GPU die. One tick, less than a billionth of a second, is slowed to about two seconds.

Design runs in five stages, all in software, and each stage's output is the next one's input.

• Architecture. Engineers fix the shape of the chip: the width of the block that multiplies numbers, the amount of fast on-chip memory beside it and the number of high-bandwidth memory stacks along the chip's edges. The output is a plan.
• RTL. Engineers write the plan as register-transfer-level code, RTL, in the hardware language SystemVerilog. A register is a small store on the chip that holds one number. On each tick of the chip's clock, every register takes its next value at the same moment. The code says what every register holds on every tick. The output is a text description of the whole chip.
• Verification. A large team checks that the code does what the plan says. They run it in simulation and prove parts of it correct with mathematics. They also load it into emulators, cabinets of reprogrammable chips that behave like the design, so the chip's own software can boot before any silicon exists.
• Physical design. Software swaps each piece of the code for a logic cell, a small ready-made circuit the foundry has already proved it can make. It then places the cells on the chip, wires them together and proves that every signal arrives in time.
• Tape-out. Engineers hand the finished layout to the foundry, a step called tape-out. Software then turns the layout into pattern files for the mask shop, in steps that run after tape-out¹⁰. First it pre-distorts each shape so that the shape prints as drawn, a step called optical proximity correction. Then it cuts the layout into the files a mask writer reads, a step called mask data preparation.

All that checking exists because each revision after tape-out, called a respin, needs at least some new masks¹. In 2022 SemiAnalysis put a full mask set at more than $1 million at 28 nm and more than $10 million at 7 nm¹. The nanometer labels name process generations, called nodes, each finer than the last, and no longer measure anything. That year SemiAnalysis also expected 3 nm sets to push into the $40 million range¹. Its May 2026 primer still puts a leading-edge mask set at $40 million, and a single leading-edge respin at $50 million to $100 million⁵.

The same 2022 SemiAnalysis article reported that startups had taken chips on TSMC 7 nm, then a leading-edge process, from design to tape-out for $50 million to $75 million, everything included¹.

Variants and trade-offs

Merchant GPU versus custom ASIC

Nvidia designs its Blackwell GPU once and sells it to everyone, so the buyer gets mature software and a resale market. A custom accelerator, an ASIC, is built for one company's own workload. It handles a narrower range of tasks and is tuned to that workload. Ironwood, the seventh-generation tensor processing unit (TPU) Google announced in April 2025, carries 192 GB of memory per chip, six times its predecessor's, and delivers twice the performance per watt¹¹. In April 2026 Google announced its eighth generation as two chips, the TPU 8t for training and the TPU 8i for inference, with up to twice Ironwood's performance per watt¹².

The EDA flow

Chip design software is known as electronic design automation, or EDA. Three complete EDA flows exist, each a set of tools that covers every step from code to signoff⁶. SemiAnalysis wrote in May 2026 that no startup can replicate one by writing it from scratch⁵. Changing the synthesis tool, which swaps the code for logic cells, means re-running the steps that follow: placing and wiring the cells, signoff and physical verification⁵. Foundries also specify which signoff tools their customers must use for tape-out⁵.

For chips at advanced nodes, 7 nm and below, one vendor holds most of the market inside some steps of the flow. Synopsys alone has more than 90 percent of the market for static timing analysis, the check that every signal arrives in time at the chip's rated speed⁵. In May 2026 SemiAnalysis put Siemens EDA's Calibre at more than 85 percent of physical verification, the final layout check⁵. It put Cadence's Palladium at 55 to 60 percent of hardware emulation⁵.

Buy the IP or build it

Design houses license ready-made circuit blocks, known as intellectual property or IP, including the processor cores, the interface controllers and the blocks that drive high-bandwidth memory. Arm licenses processor designs. In fiscal 2026 it reported $4.92 billion of revenue, $2.61 billion of it royalties⁷. It said it held about 50 percent of processor compute at the top cloud firms⁷.

In 2026 Arm also launched the Arm AGI CPU, its first production silicon product⁷. By May 2026, servers built on it could be ordered from ASRock, Lenovo, Quanta and Supermicro⁷.

The memory interface is hard to design, because its signals have to stay on time across thousands of microscopic solder bumps into a stacked memory die.

RISC-V is an open instruction set, the basic list of commands a processor understands, and it needs no license. Small RISC-V processors handle control tasks on the chip, and Nvidia uses them in every GPU¹³.

Chiplets

The reticle limit caps the size of a single die, one piece of silicon¹⁴. That limit is the largest area a scanner, the machine that prints the chip's pattern, can expose in one shot. Many large accelerators are built from chiplets, several smaller dies wired together, and UCIe is an open industry standard for the links between them inside a package¹⁵. Version 3.0 of UCIe adds faster data rates, 48 and 64 gigatransfers per second¹⁵. In a December 2024 presentation, Broadcom said its 3.5D XDSiP platform packs more than 6,000 mm2 of silicon and 12 high-bandwidth memory stacks into one package¹⁴.

Who makes it

Design software, simulation software and licensed blocks made up an $18 billion market in 2025, on SemiAnalysis's count⁵. Synopsys, Cadence and Siemens EDA took more than 85 percent of it, counting Ansys as part of Synopsys⁵. No other vendor had more than 5 percent of any core category⁵. Siemens EDA is a US-based subsidiary of the German firm Siemens¹⁶.

Synopsys is the largest. Its own results put revenue at $7.054 billion for the fiscal year to 31 October 2025, with Ansys, bought that July, contributing $756.6 million¹⁷. Cadence, whose year ends in December, took $5.297 billion in calendar 2025¹⁸.

The two fiscal years do not line up, so any total for this market depends on which twelve months are counted. It also depends on how much of Ansys it includes, because Ansys sells to other industries too. SemiAnalysis counts Synopsys at $8 billion for calendar 2025 with Ansys included⁵. On the same count Cadence is second, at $5.30 billion, and Siemens EDA third, at an estimated $2.2 billion to $2.5 billion⁵. It puts 31 percent of Ansys's business in semiconductors and high technology, 22 percent in aerospace and 18 percent in automotive⁵.

Some chip firms also build custom accelerators to a customer's design and sell the finished chips. Broadcom booked $16.7 billion of AI semiconductor revenue in the third quarter of fiscal 2026, up 221 percent year over year⁸. That figure covers both its custom AI accelerators and its AI networking chips⁸.

In October 2025 OpenAI and Broadcom said they would deploy 10 gigawatts of OpenAI-designed accelerators¹⁹. Broadcom would turn the design into silicon and supply the Ethernet networking around it¹⁹. In April 2026 Broadcom and Meta extended their partnership to multiple gigawatts of MTIA, Meta's custom chip, including what they called the industry's first 2 nm AI accelerator²⁰.

Marvell, another US firm, also builds custom AI chips to each customer's specifications²¹. Below Broadcom and Marvell are the Taiwanese design-service houses. They carry a customer's circuit list all the way to a finished mask set on TSMC's newest nodes. One of them, Alchip, reported $992 million of revenue in 2025²².

Chip design engineers are spread across more countries than these firms are. India alone has nearly 20 percent of the world's chip design engineers, the Indian government said in July 2025²³.

The chokepoint

Before the 2025 letters, a narrower control already applied. Since 14 October 2022, design software specially made for chips with gate-all-around transistors has needed a US export license for national-security reasons³. The rule calls that transistor design key to processes at 3 nm and below³. That license requirement covers exports to China²⁴. The control carried out a December 2021 decision of the Wassenaar Arrangement, a group of countries that coordinate export controls³.

In late May 2025 the US Bureau of Industry and Security, the agency that issues export licenses, told the design-software vendors that sales to China now needed a license². Cadence got its letter on 23 May². The letter required a license to export design software and technology classified 3D991 and 3E991 to any party in China, or to a Chinese military end user anywhere². Synopsys got its letter on 29 May and a second letter lifting the requirement on 2 July²⁵.

Unlike the 2022 control, the 2025 requirement came from the United States alone and took effect immediately. Synopsys's China revenue fell from 16 percent of its total in fiscal 2024 to 12 percent in fiscal 2025⁵. SemiAnalysis links the decline to tighter export restrictions and to local design-software companies winning share at mature nodes⁵. SemiAnalysis also quoted Synopsys's management saying that companies Synopsys cannot sell to look for alternatives, typically local design-software and licensed-block companies⁵.

In October 2025 CSIS found that only a few companies, Cadence, Synopsys and Siemens, make design software that supports the entire chip design flow of more than 40 steps⁶. In a January 2021 report built on 2019 market data, CSET at Georgetown University found that one Chinese firm, Empyrean, could reportedly run a complete design flow only for certain analog and mixed-signal chips²⁶. Mixed-signal chips combine analog and digital circuits. For all other chips, Chinese designers then relied on US tools²⁶. The report found that other Chinese tools covered only narrow parts of the design flow or supplemented US tools, and largely did not support processes at 14 nm and below²⁶.

In its 2025 annual report, filed in April 2026, Empyrean says it now has complete design flows for analog, memory, radio-frequency and flat-panel display circuits²⁷. It says its digital tools cover 80 percent of the main tools for digital design²⁸. The same report lists foundry certifications for its circuit simulator at 8, 5 and 4 nm and for its physical verification tool, the final layout check, at 28 nm²⁹. But CSIS found that as of 2025 Chinese design tools were still far from replacing the full range of advanced capabilities US firms offer, especially for 5 nm and 3 nm chip design⁴.

China can design accelerators, but it cannot finish one at the leading edge without foreign tools, or build what it designs without foreign equipment. SMIC, China's leading foundry, makes chips for Huawei⁹. In June 2024 CSET found that SMIC's limited 7 nm capacity forced Huawei to choose between making its most advanced phone chips and its AI chips³⁰.

On Epoch AI's estimates, Huawei's flagship chip for 2026, the Ascend 950, delivers about half the computing performance of Nvidia's H100, which began shipping in 2022⁹. Epoch puts Nvidia's B300 at 6.75 times the 950's theoretical peak performance⁹. Epoch's median estimate is that Huawei will make about 1.5 million Ascend chips in 2026, against 5.9 million for Nvidia⁹. On those estimates, Huawei's 2026 output would carry less than 4 percent of the computing power Nvidia ships that year⁹.

Epoch puts Huawei's chips three to four years behind Nvidia's until at least 2030, for three reasons⁹. SMIC cannot pack transistors as densely as TSMC, which makes Nvidia's. Chinese memory makers are only starting to produce high-bandwidth memory. And Huawei's software for programming its chips is far less mature than Nvidia's⁹.

The world market for silicon wafers was $11.4 billion in 2025, on 12,973 million square inches shipped¹⁰. That is a small fraction of Nvidia's data center revenue, which reached $193.7 billion in the fiscal year to 25 January 2026¹⁷.

How it works

From sand to wafer

1. 01Refine
2. 02Grow
3. 03Slice
4. 04Polish

Paused

Silicon starts as quartz rock. It is refined into rods so pure that metal impurities are no more than a few parts per billion.

1. Refine. Silicon starts as quartz rock. It is refined into rods so pure that metal impurities are no more than a few parts per billion.
2. Grow. The rods are melted. A seed crystal touches the melt and is drawn slowly up, turning, and the silicon freezes onto it as one long crystal.
3. Slice. A wire saw slices the crystal, called an ingot, into thin discs.
4. Polish. Each disc is ground, etched and polished to a mirror finish, flat right out to the edge.

Simplified. The ingot and the machines are not drawn to scale.

Silicon starts as quartzite, a rock that is silicon bound to oxygen. An arc furnace melts it with carbon, and the carbon takes the oxygen away as gas, leaving rough silicon metal. Refiners turn the metal into a gas, trichlorosilane, and distill it, because the impurities boil at other temperatures and separate out.

In the next step, the Siemens process, the clean gas flows over silicon filaments heated inside a bell jar. On the hot surface the gas breaks apart and its silicon settles onto the filaments. Over days the filaments thicken into gray rods of polysilicon. Everything downstream is made from those rods. Polysilicon comes in two ultra-high-purity grades, one for semiconductors and one for solar cells, and chips use the semiconductor grade¹.

A grower melts the polysilicon at about 1,420 degrees Celsius, hotter than lava, and pulls a single crystal out of it by the Czochralski method². The grower lowers a small seed crystal on the end of a rod to the surface of the melt and draws it back up, slowly turning. Silicon freezes onto the seed in the seed's own atomic pattern, and a cylinder, the ingot, grows beneath it. The pull starts with a thin neck so that flaws from the seed's first contact with the melt stay in the neck and never reach the ingot. Boron or phosphorus stirred into the melt, a step called doping, sets how readily the wafer conducts and whether negative or positive charges carry its current.

A wire saw, a web of fine wire running through abrasive, slices the ingot into discs. The maker then laps each disc, grinding both faces flat between rotating plates. It etches off the damaged surface with chemicals, then polishes the disc to a mirror with colloidal silica, a slurry of silica particles far too small to see. Almost every step throws material away.

Epitaxial wafers get one more layer of near-perfect silicon, grown on top at about 1,200 degrees Celsius². That is still hot enough to glow orange.

Variants and trade-offs

Polished versus epitaxial

A polished wafer is a doped single crystal polished to a mirror finish². An epitaxial wafer is a polished wafer with a thin layer of single-crystal silicon grown on top². The transistors are built in that layer, so flaws in it can make them leak current. SUMCO says an epitaxial wafer suits customers who need a near-perfect crystal or layers that differ in electrical resistance². SEMI, the industry association, credits the 2025 rise in shipments to AI-driven demand for advanced epitaxial wafers for logic chips and polished wafers for high-bandwidth memory¹⁰.

Silicon on insulator

In a silicon-on-insulator (SOI) wafer, a buried layer of oxide, which is glass, separates a thin working layer of silicon from the bulk beneath. Soitec says nearly all SOI wafers sold worldwide are made with its Smart Cut process¹⁸. Soitec's SOI product lines include RF-SOI for radio chips and fully depleted SOI (FD-SOI), and its markets run from mobile communications to cloud AI¹⁸. But SEMI tied the AI-driven growth in logic chips to advanced epitaxial wafers¹⁰.

Who makes it

The Center for Security and Emerging Technology (CSET) at Georgetown University named five key wafer firms in a January 2021 brief¹⁹. They were Shin-Etsu and SUMCO of Japan, GlobalWafers of Taiwan, Siltronic of Germany and SK Siltron of South Korea¹⁹. CSET also listed nine Chinese-owned producers, among them Zhonghuan, Simgui, ZingSEMI and Finland's Okmetic, but said they generated little revenue in comparison¹⁹.

As of 2018, five Chinese firms were making or planning 300 mm wafers²⁰. In its October 2025 listing prospectus, Eswin, a Chinese wafer maker, counts seven Chinese firms, itself included, making 300 mm wafers at scale²¹. Their combined capacity was 2.94 million wafers a month at the end of 2024²¹.

The chart shows shares of 2023 sales from a survey by Fuji Keizai, a Japanese research firm⁴. Japan's Ministry of Economy, Trade and Industry reproduced the figures in a December 2025 strategy deck⁴. The ministry's chart of the Fuji Keizai survey prints only Japan's 53 percent, so the other shares are read off it⁴. An earlier page of the ministry's deck prints Europe's share in the same Fuji Keizai survey as 10 percent²². The chart gives no separate share to Chinese or US companies⁴.

Siltronic's April 2026 investor presentation says the top five wafer makers serve around 75 percent of the market, based on revenue in the first three quarters of 2025³. It names the five as Shin-Etsu, SUMCO, GlobalWafers, SK Siltron and Siltronic itself³.

The wafer makers' 2025 results show strong AI demand and weak demand for chips made on older, mature nodes.

• Shin-Etsu. Shin-Etsu Chemical's electronics materials segment, which includes its wafer business, sold ¥1,015.7 billion in the year to March 2026, up 9 percent¹¹. AI-related demand stayed strong and demand in other sectors began to rise, lifting sales of silicon wafers, photoresist and photomask blanks¹¹. The segment also sells rare earth magnets and other materials, and the results release does not break out wafer sales²³. So the figure cannot be compared with the wafer revenue of the other firms listed.
• SUMCO. Sold ¥409,670 million and still lost ¥11,751 million, as operating profit fell from ¥36,924 million to ¥1,342 million²⁴. In the same year it added leading-edge 300 mm capacity and reorganized production of 200 mm and smaller wafers, where demand stayed weak¹².
• Siltronic. Lost €77.9 million on €1,346.7 million of sales while investing €369.1 million, with its new Singapore fab as the focus¹⁴.
• GlobalWafers. NT$60.6 billion of revenue, down 3.24 percent in local currency¹³.

Worldwide, the wafer area shipped rose 5.8 percent in 2025, but revenue fell 1.2 percent¹⁰. SEMI attributes the softer revenue mostly to traditional chip applications, where demand and pricing had yet to improve¹⁰.

China made 1.50 million metric tons of polysilicon, the raw material, in 2023, about 93 percent of world output¹⁵. Solar-grade material was an estimated 98 percent of that output and electronic-grade 2 percent¹⁵. The Commerce Department found in 2026 that semiconductor-grade polysilicon makes up only 2.4 percent of global production, a split close to China's⁸. These figures alone do not show whether Chinese polysilicon goes into chips.

Siltronic put the 2025 market for electronic-grade silicon at $1.4 billion, with five major suppliers, none of them Chinese: Wacker, Hemlock, OCI, Tokuyama and Mitsubishi⁶.

Siltronic of Germany describes itself as the only Western-based maker among the top five wafer makers, based on revenue in the first three quarters of 2025³. GlobalWafers opened a $3.5 billion plant in Sherman, Texas in May 2025, the first production line of its kind built in the United States in over twenty years⁷. The same day it announced another $4 billion for phases three and four in Sherman⁷. The US government had awarded it up to $406 million under the CHIPS incentives program for wafer plants in Texas and Missouri¹⁶.

Presidential Proclamation 11052, signed 6 August 2026, sets a minimum import price of $100 per kilogram for polysilicon ingots and wafers from 4 December 2026⁸. From the same date it adds an extra 15 percent duty on imported ingots and other listed products made from polysilicon⁸. A September 2026 Commerce rule meant to stop stockpiling before the duties start lists tariff code 3818.00.0040 among the products it covers²⁵. That code covers round, doped, single-crystal silicon wafers²⁶.

Commerce may approve plans to build US polysilicon, ingot, wafer or solar cell plants whose construction starts by 20 January 2029⁸. Firms with approved plans can import equipment and some of those products without the new duties⁸.

The chokepoint

China makes most of the world's polysilicon, but in 2019 its firms had only a small share of the wafer market. As of 2019 Chinese firms held under 5 percent of the wafer market and under 1 percent of the 300 mm market¹⁹. As of 2018, Chinese producers made 12 percent of the wafers for Chinese-headquartered 300 mm fabs, against 18 percent for 100 to 200 mm fabs²⁷.

Eswin, mainland China's largest maker of 300 mm wafers, says it ranked sixth in the world with about 7.7 percent of global 300 mm shipments in the first half of 2026⁵. Its October 2025 Shanghai listing prospectus, drawing on SEMI data, estimates that the five largest makers shipped 79.08 percent of 300 mm wafers in 2024²⁸. It puts Eswin at 6.01 percent and all other makers at 14.91 percent²⁸.

Making the smoothest, high-purity 300 mm wafers takes considerable know-how that is hard to write down²⁰. Customers have to qualify a new wafer plant before they buy from it, and Siltronic completed key customer qualifications at its new Singapore fab in July 2025⁹.

In SEMI figures from November 2020 cited by CSET, 99.7 percent of world fab capacity at 45 nm and below used 300 mm wafers²⁰. SEMI estimated that 300 mm wafers made up about 78.8 percent of all wafer area shipped worldwide in 2025, according to Eswin's 2025 annual report summary²⁹.

The last increase in wafer size, to 300 mm, happened in 2002³⁰. Bigger discs make printing, or photolithography, a bigger share of the processing cost³⁰. A 2013 University of Texas lecture cited by CSET put photolithography at half the cost of processing a 300 mm wafer, against a quarter for a 150 mm one³⁰. Wafers are still produced in diameters of up to 300 mm¹⁰.

Some GPU dies fill the whole area a lithography tool can print in one exposure. One fatal defect on such a die ruins far more silicon than one on a small chip. Extreme-ultraviolet printing also stays in focus over only a tiny range of heights (see Lithography), so the disc has to be flat at every point. SEMI's wafer group says the move to sub-3nm processes is raising requirements for wafer quality and consistency¹⁰.

A chip fab draws on hundreds of chemicals, gases and other materials¹. A shortage of any one of them can stop it. The French gas company Air Liquide alone supplies more than 200 molecules and roughly 50,000 cylinders a year¹⁴.

How it works

Why one missing material can stop a fab

1. 01One layer
2. 02Many wafers
3. 03One runs out
4. 04The fab stops
5. 05A new supplier

Paused

A chip is built up in layers. For each layer the wafer goes around a loop of steps like this one, and each step uses its own chemical, gas or metal.

1. One layer. A chip is built up in layers. For each layer the wafer goes around a loop of steps like this one, and each step uses its own chemical, gas or metal.
2. Many wafers. A fab runs many wafers at once, so every material is always in use. Deliveries keep each stock topped up.
3. One runs out. If one material stops arriving, the fab works through its stock.
4. The fab stops. When the stock runs out, wafers pile up at that step, and the rest of the fab stands idle.
5. A new supplier. A new supplier’s resist goes through round after round of tests in the fab. Even one that passes the first time takes seven to 17 months to approve.

Simplified diagram. Six steps and their materials stand for the many a fab uses, and each real layer uses its own mix.

The resist has to change only where the light lands. It also has to work with very little light, so the scanner, the machine that projects the pattern, can expose each patch of the wafer in milliseconds.

Since the 1990s the standard has been chemically amplified resist. In resists for 248 nm and 193 nm light, a photon absorbed in the film can free an acid molecule, and little more happens until the wafer is baked. In the bake, each acid molecule sets off hundreds of reactions around itself that turn the film soluble, so a little light does a lot of chemistry²⁰. The wash then takes away the exposed film and leaves the rest.

The 248 nm light comes from a krypton fluoride (KrF) laser. The 193 nm light comes from an argon fluoride (ArF) laser. Immersion scanners also pass it through a layer of water, which sharpens the image.

That chemistry works less well with extreme ultraviolet (EUV) light (see Lithography). An absorbed EUV photon instead knocks electrons loose, and a cascade of lower-energy secondary electrons makes the chemical changes in the resist²¹. A 13.5 nm EUV photon carries about fourteen times the energy of a 193 nm one, so the same dose of light arrives as far fewer photons. With fewer photons, random variation in where each one lands matters more. It shows up as ragged line edges and missing contact holes, the tiny holes that link one layer of a chip to the next.

Resist makers responded with metal-oxide resists, which are built on clusters with a tin-oxide core and absorb more of the EUV light than chemically amplified resists²². In 2021 the Japanese resist maker JSR agreed to buy Inpria, an Oregon maker of these resists¹⁹.

The other chemicals and gases put material on the wafer, take it off or keep it clean. Bulk gases such as nitrogen come by pipeline or from plants built at the fab, and specialty gases come in cylinders¹⁴. Silane gas carries the silicon for new layers into the chamber that holds the wafer. A plasma splits nitrogen trifluoride, and the fluorine it frees scrubs the chamber walls clean between wafers. Hydrofluoric acid cleans the wafer itself. Polishing slurries grind each new layer flat before the next goes on.

Sputtering targets are slabs of pure metal. A plasma knocks atoms off them, and the atoms settle on the wafer as thin metal films, including the barrier and seed layers for copper wiring²³. Electroplating then fills in the copper wiring itself²⁴. Filters and wafer carriers keep contamination out.

Variants and trade-offs

Each resist class is made for one kind of lithography, such as EUV, ArF immersion, ArF, KrF or i-line²⁵.

Who makes it

In a January 2021 brief, Georgetown University's Center for Security and Emerging Technology (CSET) put Japan's share of the semiconductor photoresist market at 90 percent, citing a 2019 estimate²⁵. The brief put most of the rest with US and South Korean firms²⁵. In a December 2025 strategy presentation, Japan's Ministry of Economy, Trade and Industry (METI) published figures from a separate survey by Fuji Keizai, a Japanese market research firm⁴. That survey counts sales by company nationality and puts Japanese companies at 77 percent in 2021 and 78 percent in 2023, with American and South Korean companies next⁴.

CSET's January 2021 brief lists five Japanese resist makers: JSR, Tokyo Ohka Kogyo, Shin-Etsu Chemical, Fujifilm and Sumitomo Chemical²⁶. It also lists Dongjin of South Korea, four Chinese firms and three firms it counts as American: DuPont, EMD Performance Materials and Inpria²⁶. Qnity Electronics, the former DuPont electronics business, says in its 2025 annual report that it offers lithography materials for every wavelength, including EUV²⁷. In its 2025 annual report summary, the Chinese firm Hubei Dinglong said China had yet to reach large-scale production of advanced resist for 248 nm, 193 nm or EUV printing¹⁷. The firm also said three of its own resists for 248 nm and 193 nm printing had moved into stable volume supply²⁸.

A vehicle of Japan Investment Corporation, a state-backed fund, bought 84.36 percent of JSR's shares at ¥4,350 each in a tender offer that closed on 16 April 2024¹². JSR's shares were delisted from the Tokyo Stock Exchange on 25 June 2024²⁹.

Tokyo Ohka Kogyo sold ¥139,668 million in the first half of fiscal 2026, up 25.1 percent, as strong demand for AI servers in data centers raised demand for chips¹³. Fujifilm planned to raise its polishing-slurry capacity at Kumamoto by about 30 percent from January 2025³⁰. It also scheduled new production and quality-evaluation equipment for EUV resist at Shizuoka and Pyeongtaek to start in October 2025³¹.

World sales of wafer fabrication materials reached $45.8 billion in 2025, and sales of packaging materials reached $27.4 billion¹⁰. SEMI counts silicon wafers and photomasks among wafer fabrication materials, along with resists, gases, chemicals and polishing materials¹¹.

In electronic gases, CSET named Merck, Air Products and Air Liquide as the market leaders in January 2021³². Air Liquide's electronics business sold €2,465 million in 2025, 9.1 percent of group revenue¹⁴. SK Specialty has made nitrogen trifluoride since 2001, when it became the first company to produce the gas in South Korea³³. Kanto Denka Kogyo refines its own fluorine gas and turns it into specialty gases for deposition, etching and cleaning³⁴. Stella Chemifa makes ultra-high-purity hydrofluoric acid for chipmaking³⁵. Morita Chemical Industries sells an electronic-grade hydrofluoric acid³⁶.

CSET's January 2021 brief, drawing on a 2019 report by the market research firm Mordor Intelligence, put five firms at more than 60 percent of the wet chemicals market³². Citing a 2019 report by the market research firm Market Reports World, it put DuPont and Cabot Microelectronics at about 56 percent of a $790 million market for polishing slurries²⁵. Counting by company nationality, the same Fuji Keizai survey, as published by METI, puts Japanese companies at 51 percent of polishing-slurry sales and 59 percent of high-purity cleaning-liquid sales in 2023⁴. Both shares were 49 percent in 2021⁴.

Cabot Microelectronics renamed itself CMC Materials in October 2020³⁷. The American firm Entegris completed its purchase of CMC Materials on 6 July 2022¹⁵. DuPont separated its electronics business into an independent company, Qnity Electronics, on 1 November 2025³⁸. Qnity sells polishing slurries and pads³⁹.

In sputtering targets for semiconductors, JX Advanced Metals puts its own share of the world market at about 65 percent as of fiscal 2026¹⁶.

The chokepoint

Supply at this stage has been disrupted three times since 2019, twice by governments and once by a war.

In July 2019 Japan put photoresist, hydrogen fluoride and fluorinated polyimide under individual export licenses for South Korea, so each export contract needed its own license⁵. Japan had supplied more than 90 percent of South Korea's imports of two of the three⁵. Its hydrogen fluoride exports to South Korea then fell 87.9 percent⁵. Japanese photoresist exports to South Korea did not fall, possibly in part because Japan allowed three-year bulk licenses for some resist sales in December 2019⁵.

South Korea bought more hydrogen fluoride from the United States and Taiwan and more photoresist from Belgium⁵. Production of all three chemicals rose inside South Korea⁵. The rise came both from South Korean firms and from Japanese companies' affiliates in South Korea⁵.

Researchers at Japan's Research Institute of Economy, Trade and Industry (RIETI) found that Japanese hydrogen fluoride exports to the United States rose⁵. They say some Japanese supply may have reached South Korea by way of the United States⁵. Japan ended the individual licenses on 23 March 2023, when it put exports of the three chemicals to South Korea under its bulk export license system⁴⁰.

In 2022 Russia invaded Ukraine, which supplied about 70 percent of the world's neon and 90 percent of the semiconductor-grade neon used by US industry⁴¹. Gas mixtures containing neon fill the lasers used in lithography, but EUV scanners use a tin light source instead⁴². Many chipmakers had added to their gas stockpiles after Russia annexed Crimea in 2014⁴¹. Samsung, SK hynix, Renesas and Rohm reported adequate neon supplies from China⁴¹.

At this stage, China's export controls cover metals. On 3 July 2023 China announced that exports of gallium and germanium would need licenses from 1 August¹⁸. On 3 December 2024 it said it would in principle grant no licenses to export gallium, germanium, antimony or superhard materials to the United States⁶. On 9 November 2025 it suspended that ban until 27 November 2026⁸. In February 2026 the US Geological Survey put China's share of world production of primary low-purity gallium at 99 percent⁴³.

The White House set out a trade deal with China on 1 November 2025⁴⁴. It said that under the deal China would also issue general licenses for exports of gallium, germanium and antimony for the benefit of US end users and their suppliers⁴⁴.

In the United States, germanium goes mainly into fiber optics, infrared optics, semiconductors and solar cells, and radiation detectors⁷. Of the gallium used in the United States in 2025, 73 percent went into integrated circuits built on gallium arsenide or gallium nitride⁴³. Another 26 percent went into optoelectronic devices such as LEDs and laser diodes⁴³. Gallium is recovered mostly as a byproduct of processing bauxite, the ore that aluminum is made from⁴³. Germanium comes from certain zinc ores and coal deposits, so the supply of each metal depends on another industry's economics⁴⁵.

In Europe, germanium metal averaged an estimated $4,100 a kilogram in 2025, against $1,392 in 2023, on Argus Media prices reported by the US Geological Survey⁷. US imports of the metal fell an estimated 67 percent in 2025 because of China's ban⁷. In October 2024 the US Geological Survey estimated that a total Chinese ban on gallium and germanium exports could cut US GDP by $3.4 billion⁴⁶.

A slower risk is the European Union's proposed restriction on PFAS, the long-lived fluorinated chemicals. These chemicals are used throughout a fab, from some etch gases to seals, filters and the plastic linings of chemical tanks and pipes. Most of the photoacid generators that free the acid in resist contain PFAS too⁴⁷. The Semiconductor Industry Association wrote in 2023 that photoresist needs the most rigorous qualification of any chemical a chipmaker uses, because each resist is tuned to the layers it prints⁹. The resist maker adjusts its formula over rounds of tests in the fab, and some resists have to be qualified one after another³.

The national authorities of Denmark, Germany, the Netherlands, Norway and Sweden prepared the proposal and updated it after evaluating more than 5,600 comments⁴⁸. ECHA, the EU chemicals agency, published the updated proposal on 20 August 2025⁴⁸. The updated proposal assessed options that would let electronics and semiconductor makers keep using PFAS where the risks can be controlled⁴⁸.

In March 2026 ECHA's two scientific committees backed an EU-wide restriction with targeted derogations, or exemptions⁴⁹. One committee gave its backing in a final opinion and the other in a draft, and their evaluation is due to finish by the end of 2026⁴⁹. The European Commission will decide in consultation with the member states⁴⁸.

ASML sold 327 lithography systems in 2025, 48 of them extreme ultraviolet (EUV)¹⁵. Nobody else makes EUV systems⁸.

How it works

The stencil is called a photomask, and the machine a scanner (see Photomasks and pellicles).

The wafer is coated with photoresist, a film that changes wherever light touches it. The mask holds one layer of the circuit as a pattern of clear and dark areas, drawn at four times its size on the chip. The machine shines light through the mask, shrinks the image four times with a lens, and lands it on the film.

A wash then removes the film where the light hit, or, with some films, where it did not, leaving the pattern standing on the wafer¹⁶. The film then serves as a stencil for the next step, which either etches the pattern into the layer beneath or fires ions into the open areas to change how the silicon conducts¹⁶. Then the film is stripped and the next mask goes in. Chips are made up of dozens of layers, ASML says¹⁶. Photronics, a US mask maker, says masks are typically sold in sets, with each layer's pattern on a different mask¹⁷.

How lithography prints a chip

1. 01Coat
2. 02Stencil
3. 03Shrink
4. 04Wash
5. 05Repeat

Paused

The wafer is coated with a thin film that changes wherever light touches it.

1. Coat. The wafer is coated with a thin film that changes wherever light touches it.
2. Stencil. A stencil, called a mask, holds the pattern for one layer of the chip, drawn four times larger than life.
3. Shrink. Light shines through the stencil, and a lens shrinks the image four times and lands it on the film.
4. Wash. A wash removes the film wherever the light landed, and the pattern is left on the wafer.
5. Repeat. The machine steps across the wafer, printing one patch at a time, each about the size of a postage stamp.

Simplified. The newest machines, which use extreme ultraviolet light, carry the image with mirrors in place of a lens.

The image from one mask covers a patch of up to 26 by 33 mm¹⁸. The wafer moves under the lens one patch at a time, close to a hundred patches per wafer. ASML's own wafers-per-hour rating for an EUV scanner assumes 96 of them¹⁸. Before the wafer is exposed, the machine measures alignment marks printed in earlier layers so the new layer lines up with them¹⁸. ASML rates the NXE:3400B's matched-machine overlay, a measure of that alignment, at 2 nm¹⁸. That model first shipped in 2017¹⁹.

Finer lines need shorter light. Glass and air both absorb the shortest light in use, at 13.5 nm²⁰. So an EUV scanner works in a vacuum and uses mirrors instead of lenses, and its masks are mirrors too²⁰. Deep ultraviolet (DUV) machines use light with a wavelength more than fourteen times longer¹¹. ASML calls its immersion DUV scanners the workhorses of the industry, used in high-volume manufacturing of the most advanced logic and memory chips²¹.

When one exposure cannot draw a pattern finely enough, chipmakers use multipatterning. In the litho-etch kind, the pattern is split between two or more masks printed in turn²². Each added mask brings more process steps, more cost and a risk that the parts of the pattern misalign²³. Self-aligned double and quadruple patterning (SADP and SAQP) print the lines with one exposure and then multiply them with deposition and etch steps²². In SAQP each printed line ends up as four²². Because one exposure places all those lines, they cannot misalign with each other, though a later exposure still prints blocks that break them where the circuit needs gaps²². ASML says one EUV exposure per layer cuts masks and process steps and lowers cost⁸.

Variants and trade-offs

Deep ultraviolet

Deep ultraviolet (DUV) light comes from gas lasers called excimer lasers: 248 nanometers from krypton fluoride (KrF), 193 from argon fluoride (ArF), shone through air or water¹¹. Cymer, an independently run ASML business in San Diego, makes these excimer lasers, which generate the light that scanners use to print patterns on wafers²⁴. Gigaphoton, a Komatsu company in Japan, also makes excimer lasers for lithography tools²⁵. Most of the machines sold are still DUV tools. Of the systems ASML sold in 2025, 131 were ArF immersion, 78 KrF and 16 ArF dry, all deep ultraviolet, and another 54 were older i-line tools²⁶. The i-line tools use 365 nm light from a mercury lamp, and ASML says they print features as small as 220 nm¹¹.

Reuters gives one price for the whole DUV segment, with tools costing roughly $60 million each³. In 2025, those 131 ArF immersion tools made up 42 percent of ASML's system sales and the 78 KrF tools only 4 percent²⁶. In DUV, ASML competes with Nikon and Canon, and it still holds above 80 percent of that market³. Without EUV, chipmakers build their finest layers on immersion DUV scanners, in several passes per layer⁸. From 1 September 2023, Dutch export licensing covered the most advanced of these scanners, ASML's NXT:2000i and later models²⁷.

Extreme ultraviolet

The 13.5 nm light comes from molten tin droplets shot from a generator¹¹. A laser hits each droplet twice, first with a low-intensity pulse that flattens it and then with a more powerful one that vaporizes it into plasma¹¹. The process repeats 50,000 times a second¹¹. Mirrors made by Zeiss, a German optics company, carry the light to the wafer¹. The largest are a meter across and smooth to within tens of picometers, a picometer being a thousandth of a nanometer¹.

Brighter light means more wafers an hour, and ASML demonstrated the first 1,000-watt EUV source in April 2025²⁸. Its TWINSCAN NXE:3800E ships at its full 220 wafers an hour, 37 percent more than the NXE:3600D²⁹.

High-NA EUV

High-NA scanners raise the numerical aperture (NA), a measure of how well the optics collect and focus light, from 0.33 to 0.55³⁰. That cuts the smallest printable feature from 13 nm to 8 nm³⁰. Their optics shrink the mask image four times in one direction and eight in the other, halving the patch of wafer one exposure covers and doubling the exposures per wafer³⁰. The second-generation TWINSCAN EXE:5200B runs at 175 wafers an hour, 60 percent above the EXE:5000⁸.

Reuters puts a standard EUV tool at around $200 million and a High-NA machine at an estimated $350 to $400 million³.

Intel and TSMC have chosen differently on High-NA:

• Intel Foundry says it uses High-NA in volume production for select layers of some Intel 18A products³¹. It installed the first EXE:5200B³². By September 2026 it had run more than one million wafers on High-NA tools, a count that includes tool testing and research as well as volume production³¹.
• TSMC waited, and in September 2026 said it will use High-NA in high-volume manufacturing from 2030³³.

ASML sold four High-NA (EXE) systems in 2025, against two in 2024³⁴. In its 2025 annual report, filed in February 2026, ASML said it expected High-NA to start supporting high-volume manufacturing in 2027⁴. On 8 September 2026 ASML and TSMC announced a move from 6-inch photomasks to 12-inch ones, to remove stitching constraints³³. Stitching constraints are the design limits that come from printing a large chip in two halves. They aim for a pilot line for the new masks by 2031 and for High-NA systems that use them to enter production by 2033³³.

Who makes it

ASML's net sales were EUR 32.7 billion in 2025, at a 52.8 percent gross margin¹⁵. In October 2026 it expected 2026 net sales of EUR 44 to 45 billion, at a gross margin of around 56 percent³⁵. Its 2025 annual report lists 5,100 suppliers⁴. Three of them and ASML's own San Diego site make the main parts of the EUV machine:

• Zeiss SMT, Oberkochen, makes the illumination system and the six-mirror projection optics³⁶.
• Trumpf, Ditzingen, makes the carbon dioxide drive laser, which amplifies a few watts to 40 kilowatts³⁷.
• ASML San Diego, which includes the light-source maker Cymer that ASML bought in 2013, designs the source where the laser turns tin into plasma, and builds the droplet generator²⁴.
• VDL ETG builds the frames that suspend and position the mirrors³⁸.

ASML says the production capacity of Zeiss, its sole supplier of optics, limits how many lithography systems it can build⁴.

In Japan, Nikon and Canon also make lithography tools. Nikon sold 22 new chip lithography systems in the year to March 2026, in a market it sizes at 570 units for 2025⁹. Its Precision Equipment business made an operating loss in the year to March 2026³⁹. Canon sold 234 chip lithography systems in 2025, 188 of them i-line and 46 KrF¹⁰. Its range runs from KrF scanners to i-line steppers, including some built for advanced packaging⁴⁰. Canon also makes a nanoimprint system, the FPA-1200NZ2C, which stamps the pattern instead of projecting it, down to a 14 nm linewidth⁴¹. Canon delivered one in 2024 to the Texas Institute for Electronics, to be used for research and prototypes⁴¹.

In January 2021 CSET, a research center at Georgetown University, found that the United States lacked firms in a few key parts of the chip supply chain, above all lithography tools¹².

Controls and China's answer

Export controls bar EUV from Chinese foundries⁵. In September 2025 CSIS judged that EUV remained "firmly out of reach" for China despite massive state investment⁵. For DUV scanners and other tools, the restrictions came in this order:

• Dutch national licensing of advanced DUV took effect on 1 September 2023⁴².
• A US rule published on 25 October 2023 put certain immersion scanners bound for advanced chipmaking under US export rules if they held any American content at all¹³. The rule did not apply if the country the scanners were first exported from already controlled them¹³.
• A partial license revocation by the Dutch government, disclosed by ASML on 1 January 2024, stopped shipments of NXT:2050i and NXT:2100i immersion scanners to a few Chinese customers⁴³.
• The Netherlands widened its licensing from 7 September 2024⁴². On 15 January 2025 it announced that from 1 April 2025 the license requirement would also cover a very limited number of further goods, among them specific measuring and inspection equipment⁴⁴.
• The BIS Affiliates Rule, issued by the US Bureau of Industry and Security, extended entity-list controls to affiliates owned 50 percent or more by listed entities from 29 September 2025¹⁴. BIS then suspended it until 9 November 2026⁴⁵. Exporting goods covered by US export rules to a firm on the entity list needs a US license¹⁴.
• The EU added certain Dutch controls to the EU Control List in November 2025⁴. ASML says this changed nothing for its immersion tools, because they already needed a Dutch license⁴.

China's share of ASML's net system sales fell from 41 percent in 2024 to 33 percent in 2025²⁶.

On DUV, Reuters reported in July 2026, citing one unnamed source, that Shanghai Aishengna Electronic Technology Group has started producing home-grown immersion DUV tools⁷. The firm was registered in August 2023 with 7 billion yuan of capital and two state shareholders, Shanghai Electric Holding and a Shanghai International Trust subsidiary⁷. It has no website and has taken in teams from SMEE, China's older scanner maker, and the startup Yuliangsheng⁷. SMEE is strongest in i-line, the coarsest kind of lithography tool, and even there holds only four percent of the world market⁵.

On EUV there is less evidence. Reuters reported in December 2025 that a Shenzhen team of former ASML engineers had built a prototype that made extreme ultraviolet light but had printed no chip⁶. To print a chip, a machine also needs mirrors that carry that light to the wafer, and ASML's sole supplier of those mirrors is Zeiss⁴.

The chokepoint

If ASML stopped shipping, no fab anywhere could add EUV capacity, because no other company makes EUV scanners⁸. The scanners already in fabs would keep printing only as long as they were serviced. ASML has around 10,000 customer support employees who maintain and upgrade those machines around the clock⁴⁶. Serviced this way, ASML's machines stay in use for a long time. In its 2025 annual report ASML said about 95 percent of the systems it had sold in the previous 30 years were still in use⁴. The same report warned that export controls may limit the service ASML can provide for machines already installed⁴⁷.

ASML has a chokepoint of its own. Zeiss SMT is its only supplier of lenses, mirrors and other critical optics⁴⁸. ASML says that if Zeiss could not supply them for a long period, it would effectively be unable to run its business⁴⁸.

In July 2026 ASML put its 2026 capacity at around 65 standard (low-NA) EUV scanners and said it plans to add 30 percent for 2027⁴⁹.

For AI accelerators, EUV is the point of control, because it prints the finest layers, the ones that set how densely transistors and wires pack²⁰. TSMC expects the number of layers needing High-NA to rise, driven mainly by the more complex transistors that AI chips need³³.

Each EUV layer of an AI accelerator is printed from a mask built on a blank plate. Only three companies worldwide supply those plates, and Japan's AGC is one of them⁷. Hoya, also Japanese, is another³. AGC says it is the only company in the world that takes an EUV blank all the way from the glass to the finished coating¹⁴.

How it works

How a photomask prints its pattern

1. 01The scanner
2. 02A mirror
3. 03The pattern
4. 04Wafer after wafer
5. 05One speck

Paused

A photomask is the stencil that lithography prints from, at least one for each layer of a chip. Inside the scanner, light bounces off the mask and carries its pattern down to the wafer.

1. The scanner. A photomask is the stencil that lithography prints from, at least one for each layer of a chip. Inside the scanner, light bounces off the mask and carries its pattern down to the wafer.
2. A mirror. No glass lets extreme ultraviolet (EUV) light through. So the mask for EUV layers is a mirror, built up from about forty pairs of very thin layers laid on glass, and the light bounces off it.
3. The pattern. A dark pattern drawn on the mirror soaks up the light wherever no line should print. The light that bounces back carries the pattern of one layer.
4. Wafer after wafer. The same mask prints its layer on wafer after wafer, so one plate shapes millions of chips.
5. One speck. A speck of dust on the mask prints on every wafer, until someone finds it. So a thin membrane on a frame, called a pellicle, covers the mask's patterned side and catches dust where it is too far out of focus to print.

Simplified. The mask is drawn face down, as it sits in the scanner. The mirror layers and the dark pattern are drawn far thicker than they are, and the light's path through the scanner's mirrors is cut to one bounce.

ASML says a chip's most complicated layers are made on EUV machines, while the rest can often be printed on older deep ultraviolet machines¹⁵. A mask starts as a blank, a polished plate with no pattern on it yet. For deep ultraviolet the blank is a window of quartz carrying a light-blocking film such as molybdenum silicide, and Shin-Etsu is one maker of those blanks¹⁶. For EUV the blank is a mirror of about 40 molybdenum and silicon layer pairs, 7 nm to a pair, laid on glass¹⁷. A dark tantalum film on top, called the absorber, will carry the pattern¹⁸.

The blank is coated with a sensitive film called resist. A mask writer then draws the design into the resist with electrons. A single-beam writer flashes one shape at a time, while NuFlare's multi-beam writer for the most advanced masks controls 260,000 beams at once¹⁹.

A wash removes the drawn resist. An etch then removes the blocking film or absorber wherever the resist is gone, and the rest of the resist is stripped. The plate now passes light, or reflects it, in the shape of one layer of the chip. On standard EUV scanners the pattern is drawn four times larger than it will print²⁰. An inspection tool compares the plate to the design, and a repair tool fixes the stray defects it finds.

EUV masks bring problems of their own:

• Mask 3D effects. Light strikes the mirror at a slant, and the absorber has height, so its edges cast small shadows that distort the printed shape. Software has to correct for the shadows in advance.
• Write precision. Every edge of the absorber has to sit within a few nanometers of where the design says.
• Particles. Anything on the mirror prints on every wafer until someone finds it.

High-NA scanners, the newest EUV machines, print finer lines with larger mirrors. To keep masks at their usual size, their mirrors shrink the pattern four times in one direction and eight times in the other²⁰. So each exposure covers half the area of a standard exposure, and a wafer takes twice as many exposures²⁰.

On 8 September 2026 ASML and TSMC announced a plan to move from the current 6-inch masks to 12-inch masks⁶. They expect the change to raise fab productivity, lower chipmaking costs and remove stitching constraints, the design limits that come from printing a large chip in two halves⁶. They aim to set up a 12-inch mask pilot line by 2031, so that High-NA scanners using 12-inch masks can enter advanced chip production by 2033⁶.

Variants and trade-offs

Blanks

AGC says it spent more than a decade meeting the blank's requirements, which include near-zero thermal expansion, perfectly smooth and flat surfaces and no particle contamination⁷. It says mass production began only in 2017⁷.

AGC publishes no market share figure for EUV blanks. In its data book, AGC ranks itself No.2 worldwide in EUV blanks, based on its own fiscal 2026 estimates⁸. Hoya says its share of the mask blank market is exceptionally high, and that customers may gradually start buying EUV blanks from more than one supplier³.

In April 2023 AGC said its EUV blank capacity would grow by about 30 percent in 2025¹⁴. The growth would come from a line in Fukushima, a project that METI, Japan's industry ministry, selected under a program to strengthen supply chains¹⁴. AGC also said it was aiming for more than ¥40 billion of sales in the business by 2025¹⁴. Its EUV blank sales grew 50 percent in 2023, AGC said in December 2024⁷. In February 2025 AGC reported that the sales reached ¥40 billion in 2024, a year ahead of the 2025 target²¹.

The sales then declined in 2025 and were recovering in 2026, AGC said in June 2026²². In August 2026 AGC set out capacity expansions of 20 to 50 percent across EUV blanks, polishing slurry and lens materials for lithography tools²³. It gave no separate figure for the blanks, and mass production on the added capacity is to begin in 2028²³.

Writers

An electron-beam writer draws the pattern into the resist on the blank. Multi-beam writers fire many beams at once, and Japan's NuFlare sells them for the 3 nm node¹⁹.

In September 2023 Intel called Austria's IMS Nanofabrication the established industry leader in the multi-beam mask writing tools that advanced EUV requires²⁴. Counting all electron-beam mask writers, CSET, a research center at Georgetown University, put IMS's share of a $994 million world market at 46.6 percent in 2025, using TechInsights data². NuFlare had 39.2 percent and JEOL 14.2 percent, in the same CSET analysis of TechInsights data².

Intel agreed in September 2023 to sell roughly 10 percent of IMS to TSMC at a valuation of about $4.3 billion²⁴. TSMC's subsidiary TSMC Development held that 10 percent at the end of 2024, at a fair value of $432.8 million in TSMC's accounts²⁵. Intel sold a combined 32 percent of IMS in 2023 and still held the other 68 percent on 27 December 2025²⁶.

Inspection and repair

A mask defect cuts the number of good chips on every wafer that mask prints, so masks are checked as blanks, after patterning and again at the fab. Actinic inspection uses 13.5 nm light, the wavelength of EUV lithography⁹. In 2019 Lasertec launched the world's first actinic inspection system for patterned EUV masks, the ACTIS A150⁹. In October 2025 it launched the ACTIS A200HiT series, which it says triples the A150's inspection speed⁹. Lasertec reported net sales of JPY 230,485 million in the year to June 2026²⁷.

As of 2026 KLA's Teron systems for mask shops detect pattern and particle defects on both EUV and optical masks¹³.

Zeiss makes AIMS EUV, which checks a mask in EUV light under the scanner's own imaging conditions to judge how a defect will affect printing¹¹. Zeiss calls AIMS the only system that tests how a mask will print under conditions equivalent to the scanner's¹¹. Zeiss says the tool can be extended to ASML's High-NA scanner, the EXE:5000¹¹. Zeiss also sells electron-beam repair tools that work on EUV masks²⁸.

Pellicles

A pellicle is a thin membrane on a frame above the mask. Particles land on it, too far out of focus to print, and the pattern below stays clean.

In 2022 ASML described its most advanced EUV pellicle as a membrane 13 nanometers thick that can withstand up to 500 degrees Celsius in a high vacuum²⁹. Every photon it absorbs is light that never reaches the wafer²⁹. The light crosses it twice, on the way in and on the way back off the mirror, so absorption counts double. ASML released its first EUV pellicles in 2016 and calls the pellicle one of the breakthroughs that brought EUV lithography to high-volume manufacturing²⁹.

Carbon nanotube membranes are the next step, aimed at next-generation High-NA, high-output EUV scanners³⁰. In 2020 imec, a Belgian chip research center, mounted them on masks and exposed them in an ASML NXE:3300 scanner³¹. The membranes passed up to 97 percent of the light in a single crossing, and imec found their effect on imaging low and correctable³¹.

Mitsui Chemicals began commercial production of silicon-based EUV pellicles under an ASML license in 2021³⁰. In 2024 it said it would build a carbon nanotube membrane plant at Iwakuni-Ohtake, tentatively due to finish in December 2025³⁰. In December 2025 Mitsui Chemicals said the plant was scheduled for completion in its fiscal 2025, in line with its initial plan³². The membranes are designed to pass 92 percent or more of the light and to withstand exposure power above 1 kW³⁰.

Cost and design economics

In July 2022 SemiAnalysis put mask sets above $1 million at 28 nm and above $10 million at 7 nm⁵. It expected 3 nm mask sets to reach the $40 million range⁵. Its May 2026 primer still puts a leading-edge mask set at $40 million⁴. The same primer puts a single respin, remaking a chip after a design flaw, at $50 million to $100 million at leading-edge nodes⁴.

Mask costs restrict which firms can use a node. SemiAnalysis wrote that at 5 nm and 3 nm, only firms with large wafer volume see the cost per transistor fall⁵. It wrote that more companies will lack the volume to spread the fixed cost of mask sets⁵. It expected failed chip designs to show up first among AI chip startups, which work on much tighter budgets⁵.

Who makes it

Mask making splits between chipmakers that make masks for their own use and independent merchant firms that sell to them and others¹. Photronics says that chipmakers' own shops once supplied most of the market, and that production has more recently tended to move toward the independents¹. TSMC makes masks too, and lists mask making among the services it offers besides making wafers³³.

Photronics calls itself a leading worldwide maker of masks for chips and flat panel displays¹⁰. It had $849.3 million of revenue in fiscal 2025, $615.1 million of it from chip masks¹⁰. The competitors it names in chip and display masks include Dai Nippon Printing, Hoya, Tekscend Photomask and two Chinese firms, Shenzhen Newway Photomask and Shenzhen Qingyi Photomask¹. It also competes with chipmakers' own mask shops¹.

SMIC, a Chinese foundry, runs two in-house mask shops in Shanghai that make masks for deep ultraviolet machines and older ones¹². Photronics began operating two mask plants in China, in Hefei and Xiamen, in 2019¹. Its chip mask business in Xiamen is a joint venture in which Dai Nippon Printing holds 49.99 percent¹. No Chinese firm appears in CSET's 2025 market shares for electron-beam mask writers².

The chokepoint

Mask blanks are a small, highly concentrated business. In 2019 Lasertec launched the first tool that inspects patterned EUV masks in EUV light⁹.

Pellicles already work in high-volume EUV manufacturing²⁹. But ASML says no material is completely transparent to EUV light, so any pellicle in the light's path costs customers productivity²⁹. In 2024 Mitsui Chemicals said it would set up production of carbon nanotube membranes for next-generation High-NA, high-output EUV scanners³⁰.

Applied Materials and Lam Research are the two largest deposition and etch suppliers. Applied Materials booked $28.368 billion of revenue in fiscal 2025¹⁵. Lam Research booked $23.233 billion in fiscal 2026¹⁶.

How it works

One round of deposition and etch

1. 01The wafer
2. 02Deposit
3. 03Coat
4. 04Expose
5. 05Develop
6. 06Etch
7. 07Strip
8. 08Repeat

Paused

A slice through one spot on a wafer, magnified until its layers show.

1. The wafer. A slice through one spot on a wafer, magnified until its layers show.
2. Deposit. A thin film is laid over the whole wafer.
3. Coat. A light-sensitive coating, the resist, is spun on top.
4. Expose. Light shines through a stencil and changes the resist wherever it lands.
5. Develop. A wash removes the resist the light reached, leaving the stencil’s pattern.
6. Etch. A plasma cuts straight down through the film wherever the resist is gone.
7. Strip. The leftover resist is removed. The pattern now sits in the film.
8. Repeat. Insulator fills the gaps and the next layer goes on. Making one chip takes 1,000 to 1,500 steps, the Semiconductor Industry Association estimated in 2025.

Simplified cross-section. The layers are drawn much thicker than they are.

Most etch steps, and many deposition steps, happen in a vacuum chamber that holds one wafer at a time. A pump empties the chamber of air, and a measured flow of gas comes in. A radio-frequency field, an electric field that reverses millions of times a second, turns the gas into a plasma. The field splits the gas into charged ions and into neutral fragments called radicals, which are more reactive than whole molecules¹⁷. Batch furnaces such as Tokyo Electron's TELINDY PLUS instead heat as many as 125 wafers at once, usually without plasma, for oxidation, low-pressure chemical vapor deposition and some atomic layer deposition¹⁸.

In most deposition steps, the gas carries the material the film will be made of. The molecules, or the radicals a plasma splits from them, land on the wafer and stick. The film builds up a few atoms at a time.

To coat the floor of a deep hole as thickly as its rim, the machine can work in cycles, a method called atomic layer deposition. First one gas settles in a single layer on every surface, and the pump removes the rest. Then a second gas reacts with that layer and nothing else, and the pump empties the chamber again. Each cycle adds a fraction of a layer of atoms wherever the gas reached, so the film grows as evenly on a hole's walls and floor as on its rim⁵.

For etch, the gas attacks one material and leaves the one beside it. Wherever the photoresist covers the wafer, it shields the film beneath. Wherever it does not, the radicals react with the surface and turn it into a gas, which the pump carries away. A second field pulls the ions straight down at the wafer, so the etch cuts vertically and a narrow hole keeps its width as it deepens¹⁷. When the etch reaches the material underneath, which the gas was chosen not to touch, it slows almost to a stop, and the tool ends the step.

The US export controls describe each deposition or etch tool by the process it is designed to run¹⁹.

Accenture and the Global Semiconductor Alliance estimated in 2020 that a part-finished chip can cross international borders 70 or more times on its way to the end customer¹. The Semiconductor Industry Association repeated the figure in 2025¹.

Variants and trade-offs

Deposition families

The market sizes and leading shares below are 2025 figures from Georgetown University's Center for Security and Emerging Technology (CSET), based on data from the research firm TechInsights. CSET puts the deposition tool market at $26.2 billion³. It puts the dry etch market at $21.9 billion⁸.

• Physical vapor deposition (PVD), which knocks atoms off a solid target and lands them on the wafer, was a $4.9 billion market in 2025⁹. Applied Materials held 82.4 percent of it and China's Naura 14.7 percent⁹.
• Chemical vapor deposition (CVD), which reacts gases at the wafer surface to grow a film, was an $11.2 billion market in 2025, led by Applied Materials at 47 percent²⁰. The plasma-enhanced version (PECVD) runs cooler and made up most of it, $7.5 billion²¹.
• Atomic layer deposition (ALD) lays down less than one atomic layer at a time. Each step stops once every surface is covered, so it coats vertical walls as evenly as horizontal floors. US regulators say that even coating makes it important for building 3D structures, such as 3D DRAM, 3D NAND, and the FinFET and gate-all-around transistors in logic chips⁵. ASM International leads it with 54.5 percent of a $4.1 billion market in 2025⁶.
• Epitaxy grows layers that line up with the crystal beneath them, using high-temperature CVD tools²². Electroplating deposits the copper used for wiring across the wafer²³.

Etch families

• Conductor etch, which cuts gates, metals and silicon, was a $12.2 billion market in 2025, led by Lam at 51.2 percent, by CSET's count from TechInsights data¹⁰.
• Dielectric etch, which cuts the insulating oxides and nitrides between them, was an $8.7 billion market in 2025, led by Tokyo Electron at 55.9 percent, by CSET's count from TechInsights data¹¹.
• High-aspect-ratio etch cuts the deep, narrow channels that let 3D NAND stack layers of memory cells²⁴. Lam says slight departures from a channel's intended shape can hurt yield²⁴. Lam runs this etch well below 0 degrees Celsius²⁴. It says its Cryo 3.0 technology can etch channels up to 10 microns deep whose width varies from top to bottom by less than 0.1 percent of their depth²⁴.

AI hardware needs sideways cuts, deeper holes and a second stack of metal wiring on the back of the wafer.

• Gate-all-around transistors need highly selective isotropic etch, which cuts sideways²⁵. The US Bureau of Industry and Security (BIS) controls isotropic dry etch tools that remove silicon-germanium at least 100 times faster than silicon, a selectivity of 100:1 or more¹⁹.
• HBM (high-bandwidth memory) needs holes etched straight through the silicon, called through-silicon vias (TSVs), so chips can be stacked and wired²⁶. BIS controls the tools that etch these holes at aspect ratios (depth to width) of 10:1 or more and at rates above 7 microns a minute¹³. The control covers only tools that also keep the holes' depth even to within 2 percent across the wafer¹³.
• Backside power delivery moves the wires that carry power to the back of the wafer²⁷. In July 2024 Applied Materials said it expected backside power to add $1 billion to the market for its wiring tools, for every 100,000 wafers a month of new fab capacity²⁸.

Who makes it

The industry association SEMI put world sales of chipmaking equipment at $135.1 billion in 2025, up 15 percent from $117.1 billion³⁰. Sales of wafer processing equipment, the category that includes deposition and etch tools, rose 12 percent³⁰.

No one firm dominates deposition and etch the way ASML dominates lithography. In dry etch, CSET's count for 2025 from TechInsights data puts Lam Research at 41.1 percent, Tokyo Electron at 23.4 percent and Applied Materials at 17.4 percent⁸. Tokyo Electron's own results presentation, citing Gartner, gives it 23 percent of dry etch, 27 percent of deposition systems (furnace, ALD and low-pressure CVD tools) and 15 percent of ALD in 2025²⁹. The same presentation, again citing Gartner, gives it 91 percent of coater/developers in 2025²⁹. These machines coat wafers with photoresist and develop the pattern after lithography.

ASM International, the atomic layer deposition specialist, reached a record EUR 3.2 billion of revenue in 2025 as customers built 2 nm gate-all-around capacity³¹. Molybdenum ALD, a new use of its tools that deposits the metal molybdenum, entered volume production that year³¹.

China and the controls

China is the tool vendors' largest market, buying $49.3 billion of equipment in 2025, half a percent less than in 2024³⁰. Taiwan's spending rose 90 percent to $31.5 billion³⁰. South Korea's rose 26 percent to $25.8 billion³⁰. China still takes a large share of every major vendor's sales.

• Tokyo Electron: 34.1 percent of sales in the year to March 2026, down from 41.7 percent³². It was 30.4 percent in the quarter to June 2026³³.
• Lam Research: about 34 percent of revenue in the year to June 2026, the same as a year earlier³⁴.
• Applied Materials: 28 percent in the third fiscal quarter of 2026, down from 35 percent a year earlier³⁵.
• ASM International: more than 30 percent of 2025 revenue³¹.

Between 2019 and 2024, by CSET's analysis of TechInsights data, China-based suppliers went from 2 to 7 percent of deposition and from under 3 to almost 9 percent of etch and clean¹². In ALD they gained no share and held less than 1 percent in 2024¹².

CSET's newer analysis of data that TechInsights published in July 2026 puts them at 9.8 percent of deposition in 2025³. They held 10.1 percent of etch and clean that year⁴. In dry etch alone their share was 12.4 percent⁸. In ALD they held 2.6 percent in 2025, most of it from Piotech⁶.

The Chinese toolmaker AMEC alone held 12.4 percent of dielectric etch in 2025, by CSET's count from TechInsights data¹¹. Its revenue was RMB 12.385 billion that year, up about 36.62 percent, and it spent RMB 3.744 billion on research and development, 30.2 percent of sales³⁶.

The United States tightened its export controls at least five times between 2022 and 2025.

• October 2022. The 7 October interim final rule required a license for certain chipmaking equipment, and for some activities by US persons that support the making of certain chips in China³⁷. It also extended US license rules to more foreign-made items bound for 28 Chinese entities on the Entity List, the US list of foreign firms that exporters need a license to supply³⁷.
• October 2023. The October rule, effective 17 November, rewrote the equipment entries³⁸. It added sideways (isotropic) and vertical (anisotropic) dry etch (ECCN 3B001.c.1), spatial ALD (3B001.d.9), low-fluorine tungsten ALD and CVD (3B001.d.10) and carbon hard mask PECVD (3B001.d.5)⁵.
• December 2024. BIS controlled 24 more types of equipment and three types of software, and added 140 entities to the Entity List¹⁴. The new equipment entries include TSV etch, and deposition into features with aspect ratios above 200:1³⁹. BIS also wrote a foreign direct product rule that reaches some tools built outside the United States¹⁴. The rule largely exempts foreign-made tools exported by firms located in Japan, the Netherlands and the 31 other countries it lists, whose governments can control these tools themselves⁴⁰. Japan added advanced chipmaking equipment to its control list on 23 July 2023⁴¹.
• September 2025. BIS removed the Chinese units of Samsung and SK hynix, and Intel Semiconductor (Dalian), from the Validated End-User program, effective 31 December 2025⁴². From that date, US tools bound for them need a license⁴². BIS estimated that the change would add 1,000 license applications a year⁴².
• September 2025. The Affiliates Rule extended Entity List restrictions to any company at least 50 percent owned by a listed entity⁴³. BIS then suspended it until 9 November 2026⁴⁴.

The rules apply to the toolmakers as well as to their customers. In fiscal 2026 Applied Materials took a $253 million charge to settle an export controls compliance matter with BIS³⁵.

Of the tools in the chart below, China-based suppliers have their largest share in dry stripping, which clears leftover photoresist off the wafer and was a $314.6 million market in 2025, by CSET's count from TechInsights data⁴⁵. Kokusai held 35.7 percent of it, Mattson Technology 22.6 percent and Naura 8.3 percent⁴⁵. Mattson is a US-based firm that Beijing E-Town bought in 2016¹².

The chokepoint

Deposition and etch tools are a chokepoint, but a weaker one than lithography. Most deposition and etch steps have three or four credible vendors. Atomic layer deposition has at least five⁶. The December 2024 rule targets tools for advanced atomic layer deposition and for coating holes more than 200 times deeper than they are wide⁷.

Process control tools, the machines that measure and inspect wafers and masks, were a $15.7 billion market in 2025, by CSET's count from TechInsights data². KLA puts the whole wafer equipment market, including advanced packaging, at about $120 billion that year⁶.

CSET's count for 2025, built on TechInsights data, puts KLA at 56.8 percent and Applied Materials, the next largest, at 11.2 percent². At its March 2026 investor day KLA cited Gartner's figures for 2024, which put its share at 56.5 percent, 6.5 times its nearest competitor⁸. In April 2026 KLA said its 2025 share was about 7 times the nearest competitor's⁹.

How it works

An inspection tool sweeps a beam of light across the wafer, photographs it, and compares the image of each chip with the image of its neighbors. The chips on a wafer are meant to be identical, so the tool flags anything that shows in one and not the others as a possible defect. It records where each one is. For faults too small for light to show, a second tool scans a beam of electrons across a small patch and builds a picture from the electrons the beam knocks loose from the surface.

A metrology tool measures known shapes. It shines light on a test pattern printed beside the circuits and works out from the reflected light how wide the lines are and how thick the film is. It also reads marks printed in this layer and the last to measure how far the two are out of line, which chipmakers call overlay.

The fab pays for all this to protect yield, the share of chips on a wafer that work. A wafer loses value two ways: whole regions ruined by mishandling, misalignment or over-etching, and single circuits killed by stray material or an airborne particle¹⁰.

A bigger chip is a bigger target for the second kind, so the cost of each good chip grows faster than its area¹. Chipmakers call each chip on a wafer a die. In the standard formula, die yield is (1 + D0A/a) to the power minus a. Here D0 is defects per square centimeter, A is die area, and a is a clustering constant of 3 to 4 that says how much defects bunch together. At a defect density of 0.8 per square centimeter, with a set to 3, a 1 square centimeter die yields 49.2 percent and a 2 by 2 centimeter die 11.3 percent¹. Because the bigger die yields less and fits fewer times on a wafer, it costs 20.1 times as much as the small one¹.

In another textbook example, a fab makes 5,000 wafers a week, each holding 200 dies, and earns $15 from each good die¹¹. Each percentage point of yield is then worth $7.8 million a year¹¹. Engineers raise yield by finding the process step that is losing dies and fixing it, work called yield learning.

The formula's percentages are the share of dies with no killer defect. A chip built from many identical blocks can carry spares and switch off a faulty block¹². Nvidia's full H100 design has 144 of its main computing blocks, called streaming multiprocessors, and the SXM5 version it ships has 132 turned on¹³. So the share of dies that can be sold is higher than the formula gives. But the formula shows how fast flawless dies get scarce as chips grow.

Why big chips lose more to defects

1. 01Specks land
2. 02Small chips
3. 03Big chips
4. 04The cost

Paused

Specks of dust and tiny flaws land at random on every wafer. A textbook example assumes 0.8 per square centimeter.

1. Specks land. Specks of dust and tiny flaws land at random on every wafer. A textbook example assumes 0.8 per square centimeter.
2. Small chips. Of chips 1 centimeter on a side, 49.2 percent miss every speck and come out flawless.
3. Big chips. Chips 2 centimeters on a side are bigger targets for the same specks. Only 11.3 percent come out flawless.
4. The cost. The big chip yields less and fits fewer times on a wafer, so it costs 20.1 times as much as the small one.

Simulated wafer laid out like the textbook example: 120 chips 1 centimeter on a side, or 26 chips 2 centimeters on a side. Specks land at random in loose clusters, 0.8 per square centimeter. The share of flawless chips follows the formula above, with a clustering constant of 3, as closely as whole chips allow.

Variants and trade-offs

The tools trade sensitivity against speed. All the market sizes and shares below are CSET's, for 2025, from TechInsights data².

• Defect inspection scans a whole wafer with light, or small areas of it with electrons, and compares each die against its neighbors. It is by far the largest family, at $6.7 billion, and KLA held 85.9 percent of it. ASML's HMI eScan 1100 runs 25 electron beams at once, up to 15 times the throughput of single-beam inspection tools, and finds patterning defects down to 7 nm¹⁴.
• Film and shape metrology measures how thick each film is and how flat the wafer is, without cutting it open. In this $2.6 billion family KLA held 45.6 percent, Nova 24.6 and Onto Innovation 10.9. Onto paid about $720 million in August 2026 for 27 percent of the Japanese X-ray tool maker Rigaku¹⁵.
• Mask inspection and repair has its own tools, because a defect on a mask, the stencil the circuit pattern is printed from, repeats on every die. This $2.2 billion family is one of two where KLA has a close rival. KLA held 45.9 percent, Lasertec 42 and Zeiss 10.1. Lasertec also makes actinic inspection tools, which check EUV masks with the same 13.5 nm light that prints them¹⁶. Lasertec calls its ACTIS A150 the world's first EUV patterned mask inspection system¹⁶. KLA's own actinic mask inspection tool was still at an early demo stage at its March 2026 investor day¹⁷.
• Overlay metrology measures how well this layer lines up with the one below. Its $991.4 million market was split almost evenly between KLA at 51.5 percent and ASML at 47.9.
• Critical dimension metrology, also called line-width measurement, measures how wide a printed feature came out. It is the one family Japan leads. Hitachi held 71.9 percent of this $1.2 billion market and Applied Materials 27.5.
• Electron-beam metrology resolves detail too fine for light. Applied Materials led this $1.3 billion family at 45.1 percent, with ASML at 35.6 and KLA at 18.8.

Who makes it

KLA says its share grew 3.6 percentage points from 2021 to 2025⁹. It says it gained share again in 2025 across mask, optical wafer and e-beam inspection⁹. Its revenue for fiscal 2026, the year to June 2026, was $13.579 billion, up from $12.156 billion in fiscal 2025¹⁸.

The rest are specialists, and none holds more than 11.2 percent, by CSET's count from TechInsights data for 2025². Eight of them each held more than 1 percent of the market that year².

• Applied Materials is the largest of them. It sells e-beam defect review tools, CD-SEMs (electron microscopes that measure line width) and e-beam metrology tools next to the deposition and etch tools whose work they check.
• Lasertec holds 6.4 percent, almost all of it mask inspection². Hitachi High-Tech holds 6.2 percent, most of it from CD-SEMs². ASML holds 5.9 percent through YieldStar overlay and HMI e-beam metrology².
• Nova holds 4.3 percent, through film metrology². It took $880.6 million of revenue in 2025¹⁹.
• Onto Innovation holds 2.6 percent². It took $1,005.3 million of revenue in 2025²⁰.
• Camtek holds 1.6 percent². It took $496.1 million of revenue in 2025²¹.

KLA's patterning line, which includes several metrology products and mask inspection, grew 61 percent year on year in the June 2026 quarter³. In that quarter Taiwan took 31 percent of KLA's revenue and China 26 percent³.

KLA says process control's share of spending on chipmaking equipment is still rising²². In memory chips, KLA credits the rise to higher performance specifications, less redundancy (fewer spare circuits) and more logic content in devices built for high-performance computing²³.

KLA's systems analyze data with AI and also filter out noise²³. In April 2026 KLA said it had added AI to every product line over the previous five years²³.

Packaging, AI and China

KLA says the AI build-out is making advanced packaging, and the process control it needs, more important²⁴. KLA became the largest supplier of process control tools for advanced wafer-level packaging in 2025, adding 14 percentage points of share⁹. It expects about $1.1 billion of packaging process control revenue in 2026, up more than 70 percent²⁴. In February 2026 Onto said it had signed a volume purchase agreement estimated at over $240 million with a high-bandwidth memory (HBM) maker for 2D inspection and 3D bump metrology through 2027²⁰.

Chinese makers are still small in process control, but one of them is growing fast. CSET's count, built on TechInsights data, puts all Chinese firms at 0.7 percent of the market in 2025². Skyverse (Shenzhen Zhongke Feice), a maker of wafer inspection and metrology tools, reported 2,053,298,171.74 yuan of revenue in 2025⁷. That was up 48.75 percent on 2024⁷. In its 2025 annual report Skyverse says Chinese makers still hold a low share of China's market for these tools and that KLA holds the largest share of it²⁵.

By CSET's 2025 count from TechInsights data, Chinese firms held 0.6 percent of defect inspection tools²⁶. They held 0.4 percent of line-width measurement tools in 2025²⁷. In film and shape metrology they held 2 percent in 2025, all of it from Raintree Scientific Instruments, or RSIC²⁸. They held no share of mask inspection and repair tools in 2025²⁹. Nor did they hold any share that year of the tools that inspect wafers during advanced packaging³⁰.

In October 2022 the US began requiring a license for any item subject to US export rules, process control tools included, bound for certain Chinese fabs⁴. The rule covered fabs that made logic chips at 16/14 nm or below, NAND memory with 128 or more layers, or DRAM at 18 nm half-pitch or below³¹.

A December 2024 rule added specific process control tools to the export control list. It controls tools for defect inspection and measurement of patterned 300 mm wafers if they can find defects of 21 nm or smaller³². They must do this using light with a wavelength below 400 nm, an electron beam with a resolution of 1.65 nm or better, a cold field emission source, or two or more electron-beam sources³². The same rule controls overlay metrology accurate to 0.5 nm or better if the tool is built into the track (the machine that coats and develops the light-sensitive resist) or can switch wavelengths quickly³². It also controls stand-alone wafer shape metrology that feeds corrections to immersion or EUV scanners³². A separate new entry, 3B994, covers optical film and line-width metrology for 300 mm wafers with software for measuring non-planar transistors³³.

BIS, the US Commerce Department bureau that wrote the rule, placed these tools in new entries for items it says also have legitimate uses in older chipmaking³⁴. So they carry narrower license requirements than tools built only for advanced chips³⁴. A new foreign direct product rule extends US jurisdiction to specified foreign-made chipmaking tools bound for Macau or for a Country Group D:5 destination such as China³⁵.

The chokepoint

One firm, KLA, held more than half the process control market in 2025. Every kind of process control tool also had a second maker that year, by CSET's count from TechInsights data². Several firms can build a good film metrology tool, but KLA led four of the eight kinds of process control tool in 2025, by CSET's count². KLA says its share of the whole market grew from 2021 to 2025⁹. A fab that can buy scanners and etchers but not sensitive inspection tools finds fewer of the defects that lower its yield, so its yield rises more slowly.