Transistors and the Front End

A Blackwell GPU is 208 billion switches on two dies, each the largest a lithography machine can print in one shot^[1]. Every switch has to turn on fully, turn off completely, and keep doing it for years. Making the switches is the front end of line; wiring them together is the back end.

How it works

Why the gate wraps around the channel

1. Inside a chip. An AI chip does all its work with transistors, tiny switches built into the silicon: 208 billion of them in one Nvidia Blackwell GPU. Making the switches is the front end of the factory; wiring them together comes after.
2. On. Each one is a switch. Seen end on, current flows through a strip of silicon, the channel, and the gate sits on top.
3. Off, leaking. Switching off, the gate squeezes the flow shut, but only near itself. In a tiny transistor, current still leaks through the part it cannot reach.
4. Fin. Stand the channel on edge as a fin, and the gate covers three sides. Much less gets through.
5. All around. Split it into thin sheets and wrap the gate around every side, and it shuts tight. That lets the switches keep shrinking, and smaller switches, packed tighter, are what make each new chip faster.

Simplified. The channel is seen end on, cut across the gate, with current drawn as points of light. Not to scale.

The front end builds that valve in a fixed order. First it marks where each transistor will sit and fires atoms of boron or phosphorus into the silicon there, a step called ion implantation, so that those patches conduct the way the design needs.

Next it shapes the channel, in a FinFET by etching the silicon into thin fins standing up from the wafer and laying the gate over the top and both sides of each fin, three sides instead of one. In a gate-all-around transistor the fab instead grows alternating layers of silicon and silicon-germanium, cuts the stack into a narrow bar, then dissolves the silicon-germanium away, leaving thin silicon sheets held at their ends like shelves, and fills the gaps above, below and beside each sheet with gate metal, all four sides. Before the metal goes in, a film of insulator a few atoms thick is laid over every sheet, so that the gate controls the channel without touching it. Last come the contacts, small metal plugs down to the two ends of the channel and to the gate, ready for the wiring layers above.

Each of those is a deposition, an etch or an implant of its own, and they have to run in exact order, since a sheet cannot be wrapped once the metal is on, nor the insulator added once it is buried.

Current leaks two ways, straight through the gate insulator and along the channel from end to end while the gate is off. The second is called short-channel leakage, and wrapping the gate around the channel reduces it. Three fixes deal with the two leaks:

• Better insulator. A thicker hafnium-based film, paired with a metal gate, lets fewer electrons slip straight through yet controls the channel as tightly as before. Intel replaced silicon dioxide with it at 45 nm in 2007 and said it cut leakage through the insulator more than tenfold and, with the metal gate, leakage along the channel more than fivefold^[2].
• More gate. Wrap gate metal around more sides of the channel, as fins and nanosheets do.
• Thinner channel. Thin the silicon until no current can flow where the gate cannot reach it.

Variants and trade-offs

Planar and FinFET

A planar transistor lays the gate on one side of a flat channel, and loses control as the channel shortens. A fin stands the channel on edge so the gate covers three sides, but current then comes in whole fins: a designer who needs more adds one, and nobody gets half a fin.

Gate-all-around nanosheets

A nanosheet lays the channel back down, stacks two to four thin sheets and threads gate metal around each one. The sheets can be drawn at different widths, so current comes in fine steps again. TSMC sells this as NanoFlex, which lets designers mix short cells for small area with tall cells for performance^[3].

N2 entered volume production in the fourth quarter of 2025, TSMC's first nanosheet node^[4]. TSMC rates the follow-on N2P at 18 percent more speed at the same power, 36 percent less power at the same speed, and 1.2 times the logic density of N3E^[5]. Intel's RibbonFET shipped on 18A, and 18A-P adds another 9 percent performance at the same power^[6]. Samsung began initial production of its 3 nm gate-all-around process in June 2022, more than three years before TSMC's N2^[7].

Those numbers are vendor claims until someone measures the silicon. Each foundry picks its own baseline, and none publishes a density figure that can be set against a rival's.

TSMC's published chip density gain over the baseline it names, A16 at its upper bound%

TSMC's published chip density gain over the baseline it names, A16 at its upper bound

N2P vs N3E	15 %
A16 backside power vs N2P	10 %

Source: TSMC advanced technologies, HPC platform

Backside power delivery

Power and signal share one stack of copper wiring above the transistors, where wide power rails crowd out the signal wires. Backside power grinds the wafer thin and builds a second network underneath it.

Intel shipped it first as PowerVia: on 18A, an 11 percent cut in routed area and a tenfold cut in dynamic voltage droop, the sag in supply voltage when a block of logic switches on at once^[6]. TSMC's Super Power Rail lands that network straight on each transistor's source and drain, with no buried rail between, which is harder to build and gives more: against N2P, A16 gives 8 to 10 percent more speed, 15 to 20 percent less power and up to 1.10 times the chip density^[5].

TSMC said in April 2026 that A13, a direct shrink of A14 with 6 percent area savings, and A12, which adds Super Power Rail to the A14 platform, are both scheduled to enter production in 2029^[8].

TSMC's logic roadmap beyond N2, from its own announcements

1. 2028-01-01N2U, 3-4% faster or 8-10% lower power than N2P
2. 2028-01-01A14, up to 15% faster and more than 20% denser than N2
3. 2029-01-01A13, a direct shrink of A14 for 6% area savings
4. 2029-01-01A12, the A14 platform with Super Power Rail backside power

Source: TSMC, 2026 North America Technology Symposium

CFET and what comes after

A logic gate needs two transistors that switch on opposite signals, and today they sit side by side. The research institute imec sees complementary FETs, which stack the two on top of each other, as an attractive design for logic nodes beyond 1 nm^[9].

The back end of line

Wiring is now as hard to make as the transistor. Copper seeps into the insulator around it, so every wire needs a barrier, a liner and a cap, and as the most critical wiring levels drop below a 20 nm pitch those extra layers take a large share of the wire's width^[10]. Two metals are moving into those narrow levels.

• Ruthenium shows promise for use without a barrier, which would keep the wire's resistance low^[10]. imec has demonstrated ruthenium lines at a 16 nm pitch^[11].
• Molybdenum conducts worse in bulk, 5.3 against copper's 1.68 microhm-cm, but in a thin film it beats tungsten by up to 30 percent and needs no barrier either, which is moving it into some contacts and local wiring layers^[12].

Who makes it

TSMC, Intel and Samsung build gate-all-around nodes with extreme ultraviolet lithography. SMIC builds 7 nm-class nodes without it^[13]. In July 2025 state-backed Rapidus said it had started making 2 nm prototypes at its plant in Chitose, Hokkaido, and would begin mass production in 2027^[14]. By June 2026 it had raised 424.95 billion yen in equity, the latest 150 billion yen from a state agency, and it has received government research subsidies since fiscal 2022^[15].

Node names describe nothing physical. SMIC's N+3, its third-generation 7 nm process, sets its narrowest wires 32.5 nm apart, tighter than Intel 18A's 36 nm, and reaches 113.4 million transistors per square millimeter against 107.7 for TSMC's N6^[13].

AI accelerators have usually trailed the leading edge, since a very large die comes out working reliably only on a process that has run for years. Blackwell uses a custom TSMC 4NP^[1]. AMD's MI455X, launched on 23 July 2026, lists TSMC 2 nm and 3 nm silicon^[16]. It spreads its compute across eight separate dies^[17].

SRAM, the fast memory on the logic die, is the scaling failure that hurts AI chips most. TSMC claims 22 percent more SRAM density from N3E to N2, but the gain comes mostly from the circuits around the array, and the cell that holds one bit shrinks little or not at all^[18]. See Memory and HBM.

The chokepoint

No single machine makes the front end a chokepoint. The recipe does, and a recipe is which steps run in which order on which tools. In September 2024 the United States put a worldwide license requirement on the know-how for building gate-all-around transistors, with an exception for countries that impose matching controls^[19].

China shows what that recipe costs. The third National Integrated Circuit Fund launched in May 2024 with 344 billion yuan, about $47 billion^[20], so money is not the constraint; tools are. A Shanghai state firm began building domestic immersion scanners in 2026 and planned about five that year and roughly 20 in 2027^[21]. Those are deep-ultraviolet machines, a generation behind EUV, and SMIC gets fine features out of them by printing its tightest layers in several passes. That volume keeps those lines running and comes nowhere near replacing ASML. EUV is further away: China has announced $43 billion for domestic development, and the Center for Strategic and International Studies judged in September 2025 that EUV remains firmly out of reach despite massive state investment^[22].

See Lithography and Geopolitics.

Key evaluation criteria

• Electrostatic control. How far the gate wraps the channel. It sets how much the switch leaks when off, and the lowest supply voltage it can run on.
• Density. Transistors per square millimeter, comparable only inside one foundry's own numbering and for one kind of cell.
• Interconnect resistance. Below a 20 nm wire spacing, copper wiring adds more and more delay from its resistance and capacitance^[11].
• Power delivery. The voltage lost carrying power across the die. Backside power frees area and cuts the droop tenfold^[6].
• SRAM scaling. The cell that holds one bit has barely shrunk since the 5 nm node, which caps how much cache an accelerator can afford^[18].
• Cost per transistor. No foundry publishes wafer prices, so it cannot be worked out from public figures.