Foundries and Fabs

TSMC calls a plant a GIGAFAB once it can run more than 100,000 wafers a month, each a 300 mm disc, twelve inches across^[1]. It operates six of them, and every one is in Taiwan^[2].

How it works

Inside, the work is one loop repeated for every layer. Wafers travel in a lot, a batch of 25 in a sealed pod called a FOUP that only a machine opens. An overhead track carries the pod from tool to tool. At each tool a robot lifts one wafer out, the tool does its one job, depositing a film, printing a pattern, etching it, cleaning it or measuring it, and the robot puts the wafer back. The pod moves on to the next tool, often across the building, and the loop starts again with the next layer. A chip takes hundreds of those visits, so a wafer spends months inside.

The pod keeps the wafer clean for all of that time, because the wafer never meets the room's air, and even that air is filtered until it carries almost no dust. Every design in the building runs on the same tools because each tool is set by recipe, the list of gases, temperatures and times for one step, and a foundry offers each customer the same list of recipes on shared machines. The tools run day and night, since an idle tool earns nothing. The finished wafer is tested (see Test and assembly), then cut and packaged.

TSMC, founded in 1987, pioneered the pure-play model, in which a foundry makes only its customers' products^[3]. In 2023 BCG estimated that a new fab for chips at 2 nm and below, completed in 2026, would cost $35 to $43 billion to own over ten years, 33 to 66 percent above 2023 costs^[4]. In March 2026 the Semiconductor Industry Association told the US Senate that building and equipping a leading-edge fab takes as much as $20 to $25 billion of capital^[5].

Every plant TSMC and its subsidiaries run came to more than 17 million wafers a year in 2025, counted as if each were the standard 12-inch size^[2]. The six largest plants, called gigafabs, had a combined capacity of more than 13 million^[1]. All six are in Taiwan, and the other plants are five smaller fabs in Taiwan, two fabs in China, two in the United States and one in Japan^[2].

Variants and trade-offs

Pure-play foundries

TSMC and UMC build only for others. Chips at 7 nm and below, meaning the newest processes, were 77 percent of TSMC's wafer revenue in the second quarter of 2026, split 33 percent at 5 nm, 30 at 3 nm, 11 at 7 nm and 3 at 2 nm, on revenue of $40.20 billion at a 67.7 percent gross margin^[6].

TSMC wafer revenue by node, 2Q26% of wafer revenue

2 nm33 nm305 nm337 nm1110 nm and above23

Source: TSMC 2Q26 results, filed with the SEC

Integrated device makers turned foundry

Intel and Samsung design and sell their own chips and rent out capacity too. Renting out capacity is harder for them, because customers dislike handing designs to a competitor and the company's own products take the best capacity. Intel Foundry reported $5.8 billion of segment revenue in the second quarter of 2026 and an operating loss of $2.089 billion^[7]. Only $293 million of that revenue came from outside customers, and Intel says substantially all of its foundry business still makes Intel's own products^[8].

National champions

SMIC, Hua Hong and Rapidus have government backing. SMIC's revenue rose 16.2 percent to $9.327 billion in 2025 at 93.5 percent utilization, on monthly capacity above a million wafers counted in the smaller 8-inch size, and a 21 percent gross margin^[9]. SMIC cannot buy an EUV scanner, yet it makes 7 nm-class chips on its N+2 and N+3 processes by printing the tightest layers in several passes on older deep-ultraviolet scanners^[10]. CSET reported in June 2024 that Huawei's Ascend 910B AI chip is believed to be made on N+2, and that SMIC's limited 7 nm capacity forced Huawei to choose between its most advanced phone chips and its AI chips^[11]. SemiAnalysis judged in April 2025 that most 910B and 910C chips were in fact made on TSMC's 7 nm process, from wafers Huawei bought through another company^[12]. Rapidus raised 267.6 billion yen from the Japanese government and 32 companies in February 2026 to carry it to 2 nm mass production by 2027^[13].

Mature-node capacity

Most wafers come off older lines, which make power devices, analog chips and microcontrollers and compete on price. In January 2025 the industry association SEMI forecast that foundry capacity at all nodes would rise from 11.3 million wafers a month in 2024 to a record 12.6 million in 2025, counted in the 8-inch size^[14]. Its June 2024 forecast had credited much of that growth to Intel's new foundry business and China's expansion^[15]. In July 2025 Intel scaled back its own fab plans, saying it would no longer go ahead with planned projects in Germany and Poland and would slow construction in Ohio^[16].

Capacity and cost

TSMC added $100 billion in March 2025 to the $65 billion already committed in Phoenix, for three more fabs, two packaging plants and an R&D center^[17]. In July 2026 it added another $100 billion for four more fabs at 2 nm or below, taking its total investment in Arizona to $265 billion across 12 facilities^[18]. All of TSMC's gigafabs are still in Taiwan^[2].

Some customers pay TSMC in advance to hold capacity at its fabs, and these deposits stood at NT$189.9 billion at the end of 2025, down from NT$291.1 billion a year earlier^[19]. In 2025 the four largest AI chip designers used around 90 percent of the world's CoWoS packaging capacity and HBM memory supply, against only 12 percent of advanced logic production^[20]. See Advanced packaging.

Who makes it

Intel is now partly state-owned. In August 2025 Washington bought 433.3 million newly issued Intel shares at $20.47, or $8.9 billion, for a 9.9 percent stake, paid out of $5.7 billion of unpaid CHIPS Act grants and $3.2 billion from the Secure Enclave program. The stake is passive, with no board seat, and the government agreed to vote with Intel's board on matters that need shareholder approval, with limited exceptions. The deal also came with a five-year warrant to buy a further 5 percent of Intel at $20 a share, which Washington can exercise only if Intel's ownership of its foundry business falls below 51 percent^[21].

Intel's technical position improved in 2026. It reached high-volume manufacturing on part of Panther Lake using ASML's High-NA extreme ultraviolet scanners, and put 18A-P into risk production, the trial runs a process goes through before it is signed off^[7].

Samsung broke ground in Taylor, Texas, in 2022 on a plant with an initial minimum investment of $17 billion, $6 billion of buildings and $11 billion of equipment^[22]. In December 2024 the Commerce Department awarded Samsung up to $4.745 billion of CHIPS Act funding to support more than $37 billion of planned investment in Central Texas, covering two new leading-edge logic fabs and a research fab in Taylor and an expansion of its existing plant in Austin^[23].

The chokepoint

In June 2024 SEMI forecast China at 10.1 million wafers a month in 2025, the most of any region, against Taiwan's 5.8 million out of a world total of 33.7 million^[15]. In the third-quarter 2026 update of its World Fab Forecast, SEMI projected that China would keep the largest installed capacity in 2026 and 2027^[24]. Little of China's is advanced; in 2022 South Korea and Taiwan held almost all of the world's logic capacity below 10 nm^[25]. The United States had almost no capacity below 10 nm in 2022, and in May 2024 SIA and BCG projected it would hold 28 percent of it by 2032, while new fab investment worldwide reaches around $2.3 trillion from 2024 to 2032^[25].

Installed wafer fab capacity by region, 2025, as forecast by SEMI in June 2024, all nodesmillion 8-inch-equivalent wafers per month

Installed wafer fab capacity by region, 2025, as forecast by SEMI in June 2024, all nodes

China	10.1 million 8-inch-equivalent wafers per month
Taiwan	5.8 million 8-inch-equivalent wafers per month
South Korea	5.4 million 8-inch-equivalent wafers per month
Japan	4.7 million 8-inch-equivalent wafers per month
Americas	3.2 million 8-inch-equivalent wafers per month
Europe and Mideast	2.7 million 8-inch-equivalent wafers per month
SE Asia	1.8 million 8-inch-equivalent wafers per month

Source: SEMI World Fab Forecast, June 2024

Three risks meet on one island:

• Seismic. Taiwan sits on an active plate boundary, and after an earthquake in January 2025 TSMC had to scrap a number of wafers in process^[26].
• Power. A gigafab is a large industrial load on a small island grid.
• Political. Taiwan held 69 percent of the world's logic capacity below 10 nm in 2022^[25]. In December 2025 SemiAnalysis put Taiwan's share of the world's advanced-node capacity, a term it did not tie to a node size, at over 90 percent, so a blockade or conflict would cut most of that output off from the world market at once^[27]. See Geopolitics.

Diversification is slow, and TSMC has yet to build a gigafab anywhere but Taiwan^[2].

Key evaluation criteria

• Leading-edge share. The share of revenue from the newest processes, 77 percent of TSMC's wafer revenue at 7 nm and below in the second quarter of 2026^[6].
• Yield at ramp. How many good chips a new process gives in its first year, which separates a profitable node from a subsidized one.
• Ten-year cost of ownership. $35 to $43 billion for a new 2 nm-class fab finished in 2026, in BCG's 2023 estimate, and rising^[4].
• Utilization. How full the lines run. SMIC's lines ran 93.5 percent full in 2025, at a 21 percent gross margin^[9].
• Customer concentration. A foundry owned by a chipmaker competes with its own customers, which caps who will trust it with a flagship design.
• Geographic exposure. How much of a buyer's supply sits on one island, one grid, one fault system.