Chip Supply Chain

Reference

AI Chips

The chips that train and run AI models, from the A100 of 2020 to the parts shipping in 2026. Each entry names the foundry, process node, memory supplier and packaging plant behind the chip wherever the maker or a cited source has published them.

38 chips13 makersUpdated 21 October 2026

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The interactive page draws each chip's package to scale and sets up to four chips side by side.

Specs side by side38 chips

TFLOPS counts trillions of calculations a second. FP16, FP8 and FP4 are number formats that use 16, 8 and 4 bits per number. The fewer the bits, the more calculations a chip can do.

Each figure carries the number of its source in the chip's list below.

ChipVendorAnnouncedFoundry, process nodeMemory typeMemory, gigabytesMemory suppliersPackageBandwidth, terabytes/sSpeed at FP16, TFLOPSSpeed at FP8, TFLOPSSpeed at FP4, TFLOPSPower, watts
B200BlackwellNvidia[all]United States2024[2]TSMC[1]4NP (custom N4P) · TaiwanHBM3E[10]8 stacks192[2]SK hynix, Micron[10]CoWoS-L[1]assembled by TSMC8[2]2,250[2]4,500[2]9,000[2]1,000[2]
B300 (GB300 NVL72)Blackwell UltraNvidia[all]United States2025[1]TSMC[all]4NP (custom N4P) · TaiwanHBM3E (12-high)[3]8 stacks288[1]SK hynix, Micron[9]CoWoS-L[all]assembled by TSMC8[1]2,500[1]5,000[1]15,000[1]1,400[1]
Rubin (VR200)RubinNvidia[all]United States2025[1]TSMC[2]3NP, from TSMC’s N3P (per SemiAnalysis) · TaiwanHBM4 (12-high)[all]8 stacks288[1]SK hynix, Samsung[all]CoWoS (per SemiAnalysis; variant not stated)[6]assembled by TSMC19.2[1]4,000[1]17,500[1]35,000[1]2,300[1]
H200 (China-licensed configuration)HopperNvidia[1]United States2023[1]TSMC[4]4N (custom N5-derived) · TaiwanHBM3E[7]6 stacks141[1]Micron[7]CoWoS-S[4]assembled by TSMC4.8[1]989[1]1,979[1]not supported700[1]
H20 (HGX H20, China variant)HopperNvidia[all]United States2023[all]TSMC[6]4N (custom N5-derived) · TaiwanHBM3[all]96[all]not publishedCoWoS-S[6]assembled by TSMC4[all]148[all]not publishednot supported400[all]
H800 (China variant of the H100)HopperNvidia[all]United States2023[all]TSMC[6]4N (custom N5-derived) · TaiwanHBM3[all]5 stacks80[all]not publishedCoWoS-S[6]assembled by TSMC3.35[all]989[all]1,979[all]not supported700[all]
A800 (China variant of the A100)AmpereNvidia[6]United States2022[6]TSMC[7]N7 · TaiwanHBM2e[all]5 stacks80[6]not publishedCoWoS-S[7]assembled by TSMC2.04[6]312[6]not supportednot supported400[6]
H100 (SXM5)HopperNvidia[1]United States2022[1]TSMC[2]4N (custom N5-derived) · TaiwanHBM3[8]5 stacks80[1]SK hynix[8]CoWoS-S[2]assembled by TSMC3.35[1]989[1]1,979[1]not supported700[1]
A100 (80 GB SXM)AmpereNvidia[1]United States2020[1]TSMC[2]N7 · TaiwanHBM2e[all]5 stacks80[1]not publishedCoWoS-S[2]assembled by TSMC2.04[1]312[1]not supportednot supported400[1]
Instinct MI355XCDNA 4 (MI350 series)AMD[1]United States2025[1]TSMC[all]TSMC 3 nm (8 XCDs) plus 6 nm (2 I/O dies) · TaiwanHBM3E (12-high)[3]8 stacks288[3]SK hynix, Micron, Samsung[all]not published8[3]2,516[3]5,033[3]10,066[3]1,400[3]
Instinct MI455XCDNA 5 (MI400 series)AMD[2]United States2026[2]TSMC[all]TSMC 2 nm plus 3 nm FinFET (AMD's own wording; it has not published the die-by-die split) · TaiwanHBM4[4]12 stacks432[4]SK hynix, Samsung, Micron[all]not published23.3[4]5,033[4]20,133[4]40,265[4]not published
Instinct MI325XCDNA 3 (MI300 series)AMD[1]United States2024[1]TSMC[2]N5 (8 accelerator dies) plus N6 (4 I/O dies) · TaiwanHBM3E[all]8 stacks256[1]not published3D package: 8 accelerator complex dies stacked on 4 I/O dies, with 8 HBM stacks around them[2]6[1]1,307.4[1]2,614.9[1]not supported1,000[1]
Instinct MI300XCDNA 3 (MI300 series)AMD[1]United States2023[1]TSMC[2]N5 (8 accelerator dies) plus N6 (4 I/O dies) · TaiwanHBM3[all]8 stacks192[1]not published3D package: 8 accelerator complex dies stacked on 4 I/O dies, with 8 HBM stacks around them[2]5.3[1]1,307.4[1]2,614.9[1]not supported750[1]
TPU v7 (Ironwood)TPUGoogle[all]United States2025[all]TSMC[5]N3E (per SemiAnalysis) · TaiwanHBM3E[all]8 stacks192[all]not publishednot published7.38[all]2,307[all]4,614[all]not supportednot published
TPU 8tTPUGoogle[all]United States2026[all]TSMC[1]N3 (per SemiAnalysis, for the eighth generation as a whole) · TaiwanHBM (generation not stated) plus 128 MB on-chip Vmem[all]216[all]not publishednot published6.53[all]not publishednot published12,600[all]not published
TPU 8i (Zebrafish)TPUGoogle[all]United States2026[all]TSMC[1]N3 (per SemiAnalysis, for the eighth generation as a whole) · TaiwanHBM (generation not stated) plus 384 MB on-die Vmem[all]288[all]not publishednot published8.6[all]not publishednot published10,100[all]not published
TPU v6e (Trillium)TPUGoogle[all]United States2024[all]not publishedHBM3 (per SemiAnalysis)[6]2 stacks32[all]not publishednot published1.64[all]918[all]not publishednot supportednot published
TPU v5pTPUGoogle[all]United States2023[all]not publishedHBM (Google does not state the generation)[5]95[all]not publishednot published2.77[all]459[all]459[all]not supportednot published
TPU v5eTPUGoogle[all]United States2023[all]not publishedHBM2[2]16[all]not publishednot published0.82[all]197[all]not supportednot supportednot published
TPU v4TPUGoogle[all]United States2021[all]not publishedHBM2[all]4 stacks32[all]not publishednot published1.2[all]275[all]not supportednot supported192[all]
Trainium3TrainiumAmazon (Annapurna Labs)[all]United States2025[all]TSMC[1]3 nm (AWS) · TaiwanHBM3E (12-high, 9.6 Gbps pin speed)[all]4 stacks144[all]SK hynix, Micron[all]CoWoS-R, organic thin-film interposer with 6 RDL layers on a 20-build-up-layer ABF substrate[3]4.9[all]671[all]2,517[all]2,517[all]not published
Trainium2TrainiumAmazon (Annapurna Labs)[all]United States2024[all]not publishedHBM3E, 24 GB per stack (per SemiAnalysis)[6]4 stacks96[all]not publishedCoWoS-R, two assemblies on one substrate (per SemiAnalysis)[6]2.9[all]667[all]1,299[all]not supportednot published
Maia 200MaiaMicrosoft[all]United States2026[all]TSMC[2]N3 (Microsoft says 'the latest TSMC N3 process technology'; it has not named the variant) · TaiwanHBM3E plus 272 MB on-die SRAM[all]216[all]not publishednot published7[all]1,263[all]5,050[all]10,100[all]750[all]
Maia 100MaiaMicrosoft[all]United States2023[all]TSMC[all]5 nm · TaiwanHBM2E[4]4 stacks64[all]not publishedTSMC CoWoS-S[4]assembled by TSMC1.8[all]800[all]not publishednot published500[all]
MTIA 400MTIAMeta[all]United States2026[all]not publishedHBM (generation not stated)[all]not publishednot publishedMulti-chip package; Meta states that MTIA 400 combines two compute chiplets and has not published the rest of the chiplet count[all]assembled by Broadcom (advanced packaging, per Meta)not publishednot publishednot publishednot publishednot published
MTIA 300MTIAMeta[all]United States2026[all]not publishedHBM3E (12-high)[all]6 stacks216[all]not publishedCoWoS; one compute chiplet and two network chiplets on a silicon interposer[all]6.1[all]560[all]1,120[all]not supported912[all]
MTIA v2MTIAMeta[all]United States2024[all]TSMC[all]5 nm · TaiwanLPDDR5 on the board, plus 256 MB of on-die SRAM. No HBM[all]128[all]not publishednot published0.2[all]177[all]not supportednot supported90[all]
JalapeñoOpenAI Intelligence ProcessorOpenAI with Broadcom[all]United States2026[all]TSMC[all]N3P compute die, N3E I/O chiplet (per SemiAnalysis) · TaiwanHBM4 (per SemiAnalysis)[all]not publishednot publishedCoWoS (per SemiAnalysis; variant not stated)[all]15.4[all]not publishednot published13,400[all]700[all]
Gaudi 3GaudiIntel[6]United States2024[6]TSMC[1]TSMC 5 nm · TaiwanHBM2E plus 96 MB on-die SRAM[all]8 stacks128[all]not publishednot published3.7[all]1,678[all]1,678[all]not supported900[all]
Gaudi 2GaudiIntel[6]United States2022[6]TSMC (Epoch AI; Intel names the node but not the foundry)[2]7 nm (Intel states the node in the Gaudi 3 white paper and does not name the foundry for Gaudi 2) · TaiwanHBM2E plus 48 MB on-die SRAM[all]6 stacks96[all]not publishedOCP OAM 1.1 mezzanine card (HL-225H)[2]2.45[all]432[all]865[all]not supported600[all]
WSE-3 Turbo (CS-4)Wafer Scale EngineCerebras[1]United States2026[1]TSMC[4]N5 · TaiwanOn-wafer SRAM only, no HBM[all]44[1]not publishedWafer-scale, no interposer; direct-liquid-cooled Wafer-Scale Backpack[4]assembled by Cerebras43,200[1]not publishednot publishednot publishednot published
LPULanguage Processing UnitGroq[all]United States2023[all]GlobalFoundries[all]14 nm on the first-generation GroqChip · United StatesOn-die SRAM only, no HBM. 230 MB per chip on the 14 nm GroqChip; Groq's current rack figure of 128 GB across 256 LPUs implies 500 MB per chip[all]0.23[all]not publishednot published156[all]not published1,230[all]not published215[all]
Ascend 910BAscendHuawei (HiSilicon)[all]China2022[7]SMIC (as CSET reports) and TSMC (in much of the installed base, SemiAnalysis judges)[all]SMIC N+2 7 nm class, per CSET; SemiAnalysis judges most 910B and 910C dies were actually made on TSMC N7 · ChinaHBM2E[all]64[7]not publishednot published1.6[7]400[7]not supportednot supported400[7]
Ascend 910CAscendHuawei (HiSilicon)[all]China2024[5]SMIC (intended) and TSMC (in much of the installed base)[all]SMIC N+2 7 nm class as intended; SemiAnalysis judges most 910B and 910C dies were actually made on TSMC N7 · ChinaHBM2E[all]8 stacks128[5]Samsung, SK hynix[all]Two silicon interposers on a shared organic substrate[all]3.2[5]781[5]not supportednot supported700[5]
Ascend 950PRAscend 950Huawei (HiSilicon)[all]China2025[3]not publishedHiBL 1.0, Huawei's own high-bandwidth memory[all]112[3]Huawei[all]not published1.4[3]425[3]804[3]1,561[3]600[3]
Ascend 950DTAscend 950Huawei (HiSilicon)[all]China2025[2]not publishedHiZQ 2.0, Huawei’s own high-bandwidth memory[all]144[2]Huawei[all]not published4[2]547[2]1,034[2]2,007[2]not published
Siyuan 590 (MLU590)SiyuanCambricon[1]China2023[all]SMIC[all]N+2 7 nm class · ChinaHBM (generation not disclosed)[all]80[all]not publishednot publishednot publishednot publishednot publishednot publishednot published
MTT S5000PinghuMoore Threads[1]China2025[1]not publishednot published80[1]not publishednot publishednot publishednot publishednot publishednot supportednot published

Sources216 sources for 38 chips

B200Nvidia · United States

How the speed figures are measured. Dense, no sparsity, derived from Nvidia’s HGX B200 board table (8 GPUs: 36 PFLOPS FP16/BF16 and 72 PFLOPS FP8 with sparsity, 72 PFLOPS FP4 dense). The higher-power GB200 NVL72 variant reaches 10,000 dense FP4 TFLOPS per GPU. HGX B200 baseboards carry 180 GB per GPU, under the 192 GB quoted for the chip. All three formats are supported and published. The HGX table carries FP4, FP8/FP6, INT8, FP16/BF16, TF32, FP32 and FP64 rows for the board.

  1. Nvidia Blackwell architecture page
  2. Nvidia HGX platform spec table
  3. Nvidia DGX B200 spec table
  4. Epoch AI machine learning hardware database (ml_hardware.csv)
  5. 15 CFR 742.6(b)(10), license review policy for advanced computing items (eCFR)
  6. Epoch AI: B200 cost breakdown and price
  7. Epoch AI: AI chip sales methodology, chip price and cost estimates
  8. Nvidia technical blog: Inside Nvidia Blackwell Ultra (Blackwell column: 192 GB, 8 TB/s)
  9. SemiAnalysis InferenceX B200 chip page
  10. SemiAnalysis, March 2024: Nvidia B100, B200, GB200 (SK hynix and Micron as HBM3E suppliers)
  11. Micron, March 2025: HBM3E 8-high 24 GB available for the HGX B200 and GB200 NVL72

B300 (GB300 NVL72)Nvidia · United States

How the speed figures are measured. Dense. Derived from Nvidia’s GB300 NVL72 table: 1,080 PFLOPS dense NVFP4, and 720 PFLOPS FP8/FP6 and 360 PFLOPS FP16/BF16 with sparsity, across 72 GPUs. On the HGX boards FP16 is unchanged from the B200, at 36 PFLOPS with sparsity across eight GPUs. The B300's gains over the B200 are in FP4 and in attention softmax throughput. This row is the NVL72 part. The HGX B300 baseboard is slower, at 108 PFLOPS dense FP4 across eight GPUs, or 13,500 per GPU. All three formats are supported and published.

  1. Nvidia GB300 NVL72 spec table
  2. Nvidia HGX platform spec table (HGX B300)
  3. Micron on 12-high 36 GB HBM3E
  4. Epoch AI machine learning hardware database (ml_hardware.csv)
  5. 15 CFR 742.6(b)(10), license review policy for advanced computing items (eCFR)
  6. Epoch AI: AI chip sales methodology, chip price and cost estimates
  7. Nvidia technical blog: Inside Nvidia Blackwell Ultra
  8. Micron, March 2025: HBM3E 12-high 36 GB designed into the HGX B300 NVL16 and GB300 NVL72
  9. SK hynix, October 2025: 36 GB HBM3E used in Nvidia's GB300 (OCP Global Summit)
  10. Nvidia, October 2025: key supply collaboration with Samsung for HBM3E and HBM4 (no chip named)
  11. Samsung, Q3 2025 results: HBM3E sold to all related customers (no chip named)

Rubin (VR200)Nvidia · United States

How the speed figures are measured. Dense, from Nvidia’s Vera Rubin NVL72 table. Its Rubin GPU column gives 35 PFLOPS NVFP4 and 17.5 PFLOPS FP8/FP6 for training and 4 PFLOPS FP16/BF16, all marked dense. FP16 is well under half the FP8 rate on this part. Nvidia separately quotes 50 PFLOPS per GPU of NVFP4 inference with sparsity

  1. Nvidia Vera Rubin NVL72 spec table
  2. Nvidia technical blog: Inside the Rubin GPU architecture
  3. 15 CFR 742.6(b)(10), license review policy for advanced computing items (eCFR)
  4. SemiAnalysis: Vera Rubin, extreme co-design (power profiles)
  5. SemiAnalysis: the great AI silicon shortage (process nodes)
  6. SemiAnalysis: OpenAI Jalapeño (Rubin CoWoS tape-out)
  7. Nvidia: Rubin platform launch release, January 2026 (NVLink 6 bandwidth)

H200 (China-licensed configuration)Nvidia · United States

How the speed figures are measured. Dense. Nvidia’s H200 SXM page quotes 1,979 TFLOPS BF16 and 3,958 TFLOPS FP8 with sparsity. The figures here are half of those. Hopper has no four-bit datapath. In its list of tensor-core types, Nvidia’s Hopper architecture post says “The FP8, FP16, BF16, TF32, FP64, and INT8 MMA data types are supported” and names no FP4. So the FP4 cell reads not supported.

  1. Nvidia H200 product page
  2. Federal Register: Revision to License Review Policy for Advanced Computing Commodities (effective 15 January 2026)
  3. Institute for Progress on the B30A decision
  4. Nvidia developer blog: inside the Hopper architecture
  5. White House fact sheet, January 2026: 25 percent tariff on chips such as the H200 and MI325X
  6. Nvidia Form 10-Q for the quarter ended 26 July 2026: H200 licenses, PRC restrictions and shipments
  7. Micron, February 2024: 24 GB 8-high HBM3E to be part of the Nvidia H200

H20 (HGX H20, China variant)Nvidia · United States

How the speed figures are measured. Dense, from Epoch AI’s hardware database, which records 148 TFLOPS FP16 and BF16 for the HGX H20. Nvidia has never published an H20 datasheet, and no allowed source gives a separate FP8 figure. FP8 is still supported, because the H20 is a cut-down Hopper part and Nvidia’s Hopper post lists FP8 among the supported tensor-core types. With no figure, the FP8 cell reads not published. Hopper has no four-bit datapath. In its list of tensor-core types, Nvidia’s Hopper architecture post says “The FP8, FP16, BF16, TF32, FP64, and INT8 MMA data types are supported” and names no FP4. So the FP4 cell reads not supported. Epoch AI describes the part as a slightly scaled-down H200 on every measure except arithmetic, where it reaches only about 15 percent of the H200.

  1. Epoch AI machine learning hardware database (ml_hardware.csv)
  2. Epoch AI: what did US export controls mean for China’s AI capabilities?
  3. Nvidia Form 8-K, 15 April 2025: license requirement on the H20
  4. Federal Register, 25 October 2023: TPP and performance density replace the interconnect test (govinfo PDF)
  5. SemiAnalysis: Nvidia’s new China AI chips circumvent US restrictions (public preamble only; the specification tables are behind the paywall)
  6. Nvidia developer blog: inside the Hopper architecture
  7. Epoch AI: AI chip sales methodology, chip price and cost estimates

H800 (China variant of the H100)Nvidia · United States

How the speed figures are measured. Dense, and identical to the H100. Epoch AI states that the H800 had exactly the same arithmetic performance as the H100 and records 989 TFLOPS dense FP16. The FP8 figure is the H100’s, halved from Nvidia’s sparse 3,958. Nvidia published no H800 datasheet outside China. Hopper has no four-bit datapath. In its list of tensor-core types, Nvidia’s Hopper architecture post says “The FP8, FP16, BF16, TF32, FP64, and INT8 MMA data types are supported” and names no FP4. So the FP4 cell reads not supported.

  1. CSIS: Where the Chips Fall, US export controls 2022 to 2024
  2. Epoch AI: what did US export controls mean for China’s AI capabilities?
  3. Federal Register, 13 October 2022: the rule that created ECCN 3A090 (govinfo PDF)
  4. Federal Register, 25 October 2023: TPP and performance density replace the interconnect test (govinfo PDF)
  5. CSET explainer: the Commerce Department October 2023 export control update
  6. Nvidia developer blog: inside the Hopper architecture
  7. Epoch AI machine learning hardware database (ml_hardware.csv)
  8. Epoch AI: AI chip sales methodology, chip price and cost estimates
  9. Nvidia Form 8-K, 24 October 2023: license requirements effective immediately for the A100, A800, H100, H800 and L40S
  10. Reuters, 1 February 2024: H800 servers sold for about 2 million yuan at launch a year earlier

A800 (China variant of the A100)Nvidia · United States

How the speed figures are measured. Dense, and identical to the A100. CSIS describes the A800 as a modified A100 engineered to stay below the 600 GB/s interconnect limit, and Epoch AI’s hardware database records the same 312 TFLOPS dense FP16. Nvidia never published an A800 datasheet outside China, so no vendor figure exists. Ampere has neither an eight- nor a four-bit float datapath. Nvidia’s Ampere architecture post states that “Third-generation Tensor Cores add support for TF32, BF16, FP64, INT8, INT4, and binary data types”. So the FP8 and FP4 cells read not supported.

  1. CSIS: Where the Chips Fall, US export controls 2022 to 2024
  2. Federal Register, 13 October 2022: the rule that created ECCN 3A090 (govinfo PDF)
  3. Federal Register, 25 October 2023: TPP and performance density replace the interconnect test (govinfo PDF)
  4. CSET explainer: the Commerce Department October 2023 export control update
  5. Epoch AI machine learning hardware database (ml_hardware.csv)
  6. Nvidia A100 product page and spec table
  7. Nvidia developer blog: inside the Ampere architecture
  8. Epoch AI: AI chip sales methodology, chip price and cost estimates

H100 (SXM5)Nvidia · United States

How the speed figures are measured. Dense. Nvidia’s H100 spec table quotes 1,979 TFLOPS FP16 and BF16 and 3,958 TFLOPS FP8 for the SXM part, both marked with sparsity. The figures here are half of those, and the Hopper post’s own dense table gives 1,000 and 2,000 TFLOPS. Hopper has no four-bit datapath. In its list of tensor-core types, Nvidia’s Hopper architecture post says “The FP8, FP16, BF16, TF32, FP64, and INT8 MMA data types are supported” and names no FP4. So the FP4 cell reads not supported.

  1. Nvidia H100 product page and spec table
  2. Nvidia developer blog: inside the Hopper architecture
  3. Nvidia Form 8-K, 31 August 2022: license requirement on A100 and H100 exports
  4. Federal Register, 13 October 2022: the rule that created ECCN 3A090 (govinfo PDF)
  5. Epoch AI machine learning hardware database (ml_hardware.csv)
  6. 15 CFR 742.6(b)(10), license review policy for advanced computing items (eCFR)
  7. Epoch AI: AI chip sales methodology, chip price and cost estimates
  8. SK hynix: first HBM3 supplied for the Nvidia H100 (press release, June 2022)

A100 (80 GB SXM)Nvidia · United States

How the speed figures are measured. Dense. Nvidia’s A100 spec table gives 312 TFLOPS FP16 and BF16 tensor core and 624 TOPS INT8 for both the SXM and PCIe parts. Its doubled figures (624 TFLOPS and 1,248 TOPS) are marked with sparsity. Ampere has neither an eight- nor a four-bit float datapath. Nvidia’s Ampere architecture post states that “Third-generation Tensor Cores add support for TF32, BF16, FP64, INT8, INT4, and binary data types”. So the FP8 and FP4 cells read not supported.

  1. Nvidia A100 product page and spec table
  2. Nvidia developer blog: inside the Ampere architecture
  3. Nvidia Form 8-K, 31 August 2022: license requirement on A100 and H100 exports
  4. Federal Register, 13 October 2022: the rule that created ECCN 3A090 (govinfo PDF)
  5. Federal Register, 25 October 2023: TPP and performance density replace the interconnect test (govinfo PDF)
  6. Epoch AI machine learning hardware database (ml_hardware.csv)
  7. Epoch AI: AI chip sales methodology, chip price and cost estimates

Instinct MI355XAMD · United States

How the speed figures are measured. Dense matrix across 256 compute units, checked against AMD’s datasheet: FP16 and BF16 2.5166 PFLOPS, MXFP8 and OCP-FP8 5.0332, INT8 5.0332 POPS and MXFP4 10.0663 PFLOPS. Its structured-sparsity column doubles FP16, BF16, OCP-FP8 and INT8, and reads N/A for MXFP8, MXFP6 and MXFP4. All three formats are supported and published

  1. AMD Instinct MI355X product page
  2. SemiAnalysis InferenceX MI355X chip page
  3. AMD Instinct MI355X GPU datasheet
  4. Epoch AI: AI chip sales methodology, chip price and cost estimates

Instinct MI455XAMD · United States

How the speed figures are measured. AMD’s datasheet gives these peak theoretical figures: 40,265 TFLOPS OCP MXFP4, 20,133 TFLOPS OCP MXFP6, MXFP8 and FP8, and 5,033 TFLOPS matrix FP16, BF16 and INT8. The datasheet’s separate structured-sparsity column doubles FP16, BF16 and INT8 to 10,066 TFLOPS and lists no sparsity figure for the MX formats or FP8. All three formats are supported and published.

  1. AMD press release: Advancing AI 2026 full-stack compute
  2. AMD Instinct MI455X product page
  3. AMD: Introducing CDNA 5 and the Helios rackscale solution
  4. AMD Instinct MI455X GPU datasheet
  5. 15 CFR 742.6(b)(10), license review policy for advanced computing items (eCFR)
  6. SemiAnalysis: Vera Rubin, extreme co-design (TCO comparison with MI4XX)
  7. SemiAnalysis: the great AI silicon shortage (process nodes)

Instinct MI325XAMD · United States

How the speed figures are measured. Dense, from AMD’s footnote MI325-002: 1,307.4 TFLOPS FP16, 1,307.4 TFLOPS BF16, 2,614.9 TFLOPS FP8 and 2,614.9 TOPS INT8. These match the MI300X, because the MI325X is the same CDNA 3 silicon with faster, larger memory. AMD’s sparsity column doubles each figure. CDNA 3 has no four-bit datapath. AMD’s CDNA 3 white paper tabulates every matrix type the architecture runs (Matrix FP64, FP32, TF32, FP16, BF16, FP8 and INT8), and the string FP4 appears nowhere in the document. So the FP4 cell reads not supported.

  1. AMD Instinct MI325X product page and specification list
  2. AMD: Introducing the CDNA 3 architecture (white paper)
  3. Federal Register, 15 January 2026: case-by-case review below 21,000 TPP (govinfo PDF)
  4. Epoch AI machine learning hardware database (ml_hardware.csv)
  5. Epoch AI: AI chip sales methodology, chip price and cost estimates

Instinct MI300XAMD · United States

How the speed figures are measured. Dense, from AMD’s own footnote MI300-17: 1,307.4 TFLOPS FP16, 1,307.4 TFLOPS BF16, 2,614.9 TFLOPS FP8 and 2,614.9 TOPS INT8 at 2,100 MHz across 304 compute units. The CDNA 3 white paper tabulates the same figures. AMD’s separate structured-sparsity column doubles each of those. CDNA 3 has no four-bit datapath. AMD’s CDNA 3 white paper tabulates every matrix type the architecture runs (Matrix FP64, FP32, TF32, FP16, BF16, FP8 and INT8), and the string FP4 appears nowhere in the document. So the FP4 cell reads not supported.

  1. AMD Instinct MI300X product page and specification list
  2. AMD: Introducing the CDNA 3 architecture (white paper)
  3. Federal Register, 25 October 2023: TPP and performance density replace the interconnect test (govinfo PDF)
  4. Federal Register, 15 January 2026: case-by-case review below 21,000 TPP (govinfo PDF)
  5. Epoch AI machine learning hardware database (ml_hardware.csv)
  6. Epoch AI: AI chip sales methodology, chip price and cost estimates
  7. SemiAnalysis InferenceX MI300X chip page

TPU v7 (Ironwood)Google · United States

How the speed figures are measured. Google’s Cloud TPU documentation gives peak per-chip compute of 2,307 TFLOPS BF16 and 4,614 TFLOPS FP8, the only two precisions the tpu7x table carries. These are dense. Google publishes no sparsity figures, and the four SparseCores are engines for embedding lookups. Four-bit arithmetic arrives with the next generation. Google’s eighth-generation deep dive says “TPU 8t introduces native 4-bit floating point (FP4)”, so the FP4 cell reads not supported.

  1. Google Cloud TPU v7 (tpu7x) documentation
  2. Google blog: Ironwood, the first TPU for the age of inference
  3. Google blog: Ironwood is generally available
  4. Google Cloud blog: inside the Ironwood TPU and its co-designed stack
  5. Google Cloud: TPU 8t and TPU 8i technical deep dive
  6. Epoch AI: AI chip sales methodology, chip price and cost estimates
  7. SemiAnalysis: the great AI silicon shortage (process nodes)

TPU 8tGoogle · United States

How the speed figures are measured. Google publishes a 12.6 PFLOPS FP4 peak and no other precision for this part, and does not say whether it is dense or sparse. It says TPU 8t “introduces native 4-bit floating point (FP4)”, doubling the throughput of its matrix multiply units. It publishes no list of other formats, so the FP16 and FP8 cells read not published

  1. Google Cloud: TPU 8t and TPU 8i technical deep dive
  2. Google blog: eighth-generation TPUs for the agentic era
  3. SemiAnalysis: the great AI silicon shortage (process nodes)

TPU 8i (Zebrafish)Google · United States

How the speed figures are measured. Google publishes a 10.1 PFLOPS FP4 peak and no other precision for this part, and does not say whether it is dense or sparse. FP4 is the only format Google names for either eighth-generation chip, and it publishes no list of supported data types. Nothing shows whether the hardware carries FP16 and FP8 paths, so those cells read not published. Third-party FP8 and BF16 numbers in circulation are derived by halving and are not official.

  1. Google Cloud: TPU 8t and TPU 8i technical deep dive
  2. Google blog: eighth-generation TPUs for the agentic era
  3. SemiAnalysis: the great AI silicon shortage (process nodes)

TPU v6e (Trillium)Google · United States

How the speed figures are measured. Google’s v6e documentation gives 918 TFLOPs peak bf16 per chip and 1,836 TOPs peak Int8, both dense, and lists no FP8 row. The eight-bit figure is INT8, so it stays in this note and out of the FP8 field. Two Google pages disagree about whether the part has an FP8 path at all. The tpu7x table prints “Peak compute per chip (FP8) (TFLOPs) … 918” for v6e, which is the bf16 figure repeated, with no gain in throughput. Nothing settles it, so the FP8 cell reads not published. No Google page gives v6e a four-bit rate, and Google dates native FP4 to the eighth generation, so the FP4 cell reads not supported.

  1. Google Cloud TPU v6e (Trillium) documentation
  2. Epoch AI machine learning hardware database (ml_hardware.csv)
  3. Federal Register, 25 October 2023: TPP and performance density replace the interconnect test (govinfo PDF)
  4. Google Cloud TPU v7 (tpu7x) documentation, which tabulates v5p, v6e and TPU7x side by side
  5. Epoch AI: AI chip sales methodology, chip price and cost estimates
  6. SemiAnalysis: TPUv7, Google takes a swing at the king (v6e and v5p node, v6e memory)

TPU v5pGoogle · United States

How the speed figures are measured. Google’s v5p table gives 459 TFLOPs peak per chip for BF16 and the same 459 TFLOPs for FP8. Dropping to eight-bit gives no extra throughput on this part, unlike the Blackwell and CDNA generations. Google still prints the FP8 row, so the format is supported and published. Both figures are dense. Google publishes no sparsity numbers. No Google page gives the v5p a four-bit rate and Google dates native FP4 to the eighth generation, so the FP4 cell reads not supported. Capacity is quoted in GiB.

  1. Google Cloud TPU v5p documentation
  2. Epoch AI machine learning hardware database (ml_hardware.csv)
  3. Federal Register, 25 October 2023: TPP and performance density replace the interconnect test (govinfo PDF)
  4. Epoch AI: AI chip sales methodology, chip price and cost estimates
  5. SemiAnalysis: TPUv7, Google takes a swing at the king (v6e and v5p node, v6e memory)

TPU v5eGoogle · United States

How the speed figures are measured. Google’s v5e table gives 197 TFLOPs peak bf16 per chip and 393 TOPs peak Int8, both dense, and no other precision. The eight-bit path is INT8, so eight-bit work on a v5e runs as integer quantization with no eight-bit floating-point path in hardware. The FP8 cell therefore reads not supported. No Google page gives this part a four-bit rate either, and Google dates native FP4 to the eighth generation. Google’s v5e table of May 2024 gave the memory as 16 GB of HBM2 at 819 GBps, and the memory fields above carry those figures. The current table names no HBM generation and lists the bandwidth as 800 GiBps.

  1. Google Cloud TPU v5e documentation
  2. Google Cloud TPU v5e documentation, archived copy last updated 9 May 2024 (HBM2, 819 GBps)
  3. Epoch AI machine learning hardware database (ml_hardware.csv)
  4. Federal Register, 25 October 2023: TPP and performance density replace the interconnect test (govinfo PDF)
  5. CSET explainer: the Commerce Department October 2023 export control update
  6. Epoch AI: AI chip sales methodology, chip price and cost estimates
  7. Google Cloud TPU v6e (Trillium) documentation (performance per TCO of 1)

TPU v4Google · United States

How the speed figures are measured. Google gives a single figure, “275 teraflops (bf16 or int8)” per chip, and names no other format. Eight-bit math runs no faster than bf16 on this part, and the eight-bit path is integer. There is no FP8 and no FP4 datapath, so both cells read not supported. Memory capacity is quoted as 32 GiB.

  1. Google Cloud TPU v4 documentation
  2. Epoch AI machine learning hardware database (ml_hardware.csv)
  3. Federal Register, 25 October 2023: TPP and performance density replace the interconnect test (govinfo PDF)
  4. Epoch AI: AI chip sales methodology, chip price and cost estimates
  5. Google (ISCA 2023): TPU v4, an optically reconfigurable supercomputer

Trainium3Amazon (Annapurna Labs) · United States

How the speed figures are measured. Dense, from the AWS Neuron architecture docs: 671 TFLOPS dense BF16/FP16/TF32 (2,517 with 4x structured sparsity), and 2,517 TFLOPS for MXFP8 and MXFP4 alike. FP4 runs no faster than FP8 on this part, but the datapath exists and AWS publishes the figure.

  1. AWS Neuron documentation: Trainium3 architecture
  2. AWS: Amazon EC2 Trn3 UltraServers now generally available
  3. SemiAnalysis: AWS Trainium3 deep dive
  4. Epoch AI machine learning hardware database (ml_hardware.csv)

Trainium2Amazon (Annapurna Labs) · United States

How the speed figures are measured. Dense, from the AWS Neuron architecture docs: eight NeuronCore-v3 deliver 1,299 FP8 TFLOPS, 667 BF16, FP16 and TF32 TFLOPS, and 181 FP32 TFLOPS, with 2,563 TFLOPS quoted for the sparse case. The page documents only those five types: FP8, BF16, FP16, TF32 and FP32. No four-bit type appears, so the FP4 cell reads not supported. MXFP4 arrives one generation later, on Trainium3.

  1. AWS Neuron documentation: Trainium2 architecture
  2. AWS Neuron documentation: Trn2 instance and UltraServer architecture
  3. Epoch AI machine learning hardware database (ml_hardware.csv)
  4. Federal Register, 25 October 2023: TPP and performance density replace the interconnect test (govinfo PDF)
  5. Epoch AI: AI chip sales methodology, chip price and cost estimates
  6. SemiAnalysis: AWS Trainium3 deep dive (Trainium2 package, node and memory)
  7. Amazon: AWS activates Project Rainier

Maia 200Microsoft · United States

How the speed figures are measured. Microsoft’s architecture deep dive gives 10.1 PetaOPS FP4 and says FP4 throughput on Maia 200 is 2x that of FP8 and 8x that of BF16. That gives 5,050 TFLOPS FP8 and 1,263 TFLOPS BF16. Microsoft's launch post says “over 10 petaFLOPS” FP4 and “over 5 petaFLOPS” FP8. Epoch AI’s database uses the same arithmetic and records 1,268 TFLOPS BF16. All three formats are supported. Microsoft does not say whether the figures are dense or sparse, and publishes no separate tensor-core FP16 rate.

  1. Microsoft: Maia 200, the AI accelerator built for inference
  2. Microsoft: Deep dive into the Maia 200 architecture

Maia 100Microsoft · United States

How the speed figures are measured. Dense, from Microsoft’s Hot Chips 2024 deck, which gives peak dense tensor throughput of 0.8 POPS at BF16. The eight- and four-bit cells read not published, because the tensor unit runs Microsoft’s own 9-bit and 6-bit MX formats, which are neither FP8 nor FP4.

  1. Microsoft Azure blog: Azure Maia for the era of AI
  2. Epoch AI machine learning hardware database (ml_hardware.csv)
  3. Federal Register, 25 October 2023: TPP and performance density replace the interconnect test (govinfo PDF)
  4. Microsoft Tech Community: Inside Maia 100 (memory, package, die)
  5. Microsoft at Hot Chips 2024: Maia 100 (deck)

MTIA 400Meta · United States

How the speed figures are measured. Meta’s blog gives only ratios to MTIA 300: 400 percent higher FP8 FLOPS and 51 percent higher HBM bandwidth. It publishes no absolute figure for either part, so the ratios cannot be turned into numbers. Meta writes that MTIA 400 “supports enhanced versions of MX8 and MX4, which are important low-precision formats”, so the eight- and four-bit cells both read not published. It names no 16-bit rate or type for this generation. The absolute figures Meta showed at Hot Chips 2026 are in a deck that requires registration.

  1. Meta AI blog: MTIA, scale AI chips for billions
  2. Engineering at Meta: MTIA 300, Meta's first training chip with built-in NICs
  3. Meta: partnership with Broadcom

MTIA 300Meta · United States

How the speed figures are measured. From the spec table in Meta’s ISCA 2026 paper: 1,120 TFLOPS FP8 and 560 TFLOPS FP16/BF16. The paper does not say whether these are dense or sparse. It says MTIA 300 has no native datapath for four-bit formats such as MX4 and runs them in software instead, so the FP4 cell reads not supported. Epoch AI’s MTIA 300 row (1,200 FP8, 600 BF16, 800 W) does not match Meta’s paper, so the table does not use it.

  1. Meta (ISCA 2026): MTIA 300, Meta’s first training chip featuring built-in NICs and collective offloading engines
  2. Engineering at Meta: MTIA 300, Meta’s first training chip with built-in NICs
  3. Meta AI blog: MTIA, scale AI chips for billions

MTIA v2Meta · United States

How the speed figures are measured. Dense. Meta’s table gives 354 TOPS INT8 and 177 TFLOPS FP16 and BF16 for the matrix engines at 1.35 GHz, with 708 and 354 quoted for the sparse case. The vector core adds 11.06 TOPS INT8, 5.53 TFLOPS FP16 and 2.76 TFLOPS FP32. Apart from FP32 on the vector core, the table carries only INT8 and FP16/BF16. There is no FP8 and no FP4 datapath, so both cells read not supported.

  1. Meta AI blog: our next-generation Meta training and inference accelerator
  2. Federal Register, 25 October 2023: TPP and performance density replace the interconnect test (govinfo PDF)
  3. Meta (ISCA 2026): MTIA 300 paper, with MTIA v2 (MTIA-2i) for comparison

JalapeñoOpenAI with Broadcom · United States

How the speed figures are measured. OpenAI publishes no per-precision FLOPS and argues that performance per unit of power is the more useful standard. SemiAnalysis gives 13.4 PFLOPS of MXFP4 for the B0 stepping (chip revision), a theoretical peak with no dense or sparse basis stated. OpenAI's own results show MXFP4 models running on the chip. FP16 and FP8 read not published. On SemiAnalysis’s InferenceX benchmark, OpenAI reports peak interactivity of 1,459 tokens per second per user on GPT-OSS 120B, 700 on DeepSeek R1 and 694 on Kimi K2.5.

  1. OpenAI and Broadcom announce a 10 GW collaboration
  2. SemiAnalysis InferenceX: Jalapeno measured against Blackwell
  3. OpenAI: Jalapeno first results

Gaudi 3Intel · United States

How the speed figures are measured. Intel’s Gaudi 3 white paper gives 1,678 TFLOPS for both FP8 and BF16 on the matrix engines, in its comparison with Gaudi 2 and again in Table 5. Table 5 also lists 459 TFLOPS for FP16 (signed) and TF32, and 229 for FP32. Epoch AI records the same 1,678. Intel’s Gaudi documentation gives 1.8 PFLOPS for FP8 and BF16 across 8 matrix multiplication engines and 64 tensor processor cores on two compute dies. Neither Intel source says whether the figures are dense or sparse. Gaudi 3 has no four-bit datapath. The white paper states that “the Intel Gaudi 3 AI accelerator MME supports all the key AI compute datatypes: FP8 (both E4M3 and E5M2), BF16, FP16, TF32 and FP32” and never mentions FP4, so the FP4 cell reads not supported.

  1. Intel Gaudi architecture documentation
  2. Intel Gaudi 3 white paper landing page
  3. Epoch AI machine learning hardware database (ml_hardware.csv)
  4. 15 CFR 742.6(b)(10), license review policy for advanced computing items (eCFR)
  5. Intel Gaudi 3 AI accelerator white paper (PDF)
  6. Intel newsroom: Gaudi kit prices (press release, 12 June 2024)
  7. Intel newsroom, 14 October 2025: Crescent Island data center GPU

Gaudi 2Intel · United States

How the speed figures are measured. Intel publishes no Gaudi 2 datasheet of its own. Its Gaudi 3 white paper tabulates the two parts together and gives Gaudi 2's matrix engines (MME) 432 TFLOPS BF16 and 865 TFLOPS FP8, the figures shown above. Epoch AI’s hardware database carries 450 TFLOPS BF16 and the same 865 FP8, but the table uses Intel’s figure. Neither source says whether the figures are dense or sparse. The Gaudi documentation lists the types: “Gaudi 2 supports all popular data types required for deep learning: FP32, TF32, BF16, FP16 & FP8 (both E4M3 and E5M2)”, with no four-bit format, so the FP4 cell reads not supported.

  1. Intel Gaudi 2 AI accelerators white paper
  2. Intel Gaudi architecture documentation
  3. Intel Gaudi 3 AI accelerator white paper (states the Gaudi 2 node)
  4. Epoch AI machine learning hardware database (ml_hardware.csv)
  5. Federal Register, 25 October 2023: TPP and performance density replace the interconnect test (govinfo PDF)
  6. Intel newsroom: Gaudi kit prices (press release, 12 June 2024)

WSE-3 Turbo (CS-4)Cerebras · United States

How the speed figures are measured. Cerebras quotes 250 PFLOPS of AI compute per WSE-3 Turbo, double the original WSE-3. It names no precision and no dense or sparse basis for the figure, so it fits none of the table's speed rows. Cerebras’s developer documentation says “The CS system offers support for the following data formats” and lists FP32, FP16, cbfloat16 and bfloat16. So FP16 is supported, with no published figure. But that page documents the training software for the CS platform and predates the CS-4. Cerebras publishes no data-type list for the WSE-3 Turbo, so the FP8 and FP4 cells read not published.

  1. Cerebras WSE-3 product page
  2. Cerebras: Introducing the CS-4
  3. Cerebras CS-4 system page
  4. Cerebras: Ultrafast frontier inference, the Hot Chips 2026 deep dive
  5. Cerebras developer documentation: supported precisions and data formats

LPUGroq · United States

How the speed figures are measured. Derived from a rack figure. Groq quotes 315 PFLOPS of FP8 inference compute and 40 PB/s of SRAM bandwidth per 256-LPU rack, which works out to about 1,230 TFLOPS FP8 and 156 TB/s per accelerator. Groq does not say whether the figure is dense or sparse. FP16 is supported, but no current figure exists. Epoch AI records 188 TFLOPS FP16 and 750 TOPS INT8 for the first-generation GroqChip, from a Groq product brief whose link no longer works. Mixing that generation’s figures with a rack-derived FP8 figure would misstate the part, so the FP16 cell stays empty. Groq names no four-bit format anywhere, but publishes no data-type list either, so FP4 reads not published. Groq’s own LPU page puts on-chip SRAM bandwidth at “upwards of 80 terabytes per second”, roughly half the rack-derived figure. The two Groq pages disagree, and both are recorded here.

  1. Groq: what an LPU is
  2. Groq inference hardware page (rack-level figures)
  3. SemiAnalysis: Groq inference tokenomics
  4. Epoch AI machine learning hardware database (ml_hardware.csv)
  5. Groq: ISCA 2020 paper on the first-generation chip

Ascend 910BHuawei (HiSilicon) · China

How the speed figures are measured. CSET puts the second-generation Ascend 910B series at a theoretical maximum of 400 TFLOPS FP16, 80 TFLOPS above the first-generation 910. CSET finds that only about 75 percent of that gain is real hardware. Half of the gain comes from a higher clock, a quarter from an extra vector unit per AI core, and the last quarter from a change in how Huawei counts peak performance. Huawei publishes no per-chip figure of its own. Its Atlas 800T A2 server gives 3.0 or 2.5 PFLOPS FP16 across eight NPUs, which is 375 or 312.5 TFLOPS per chip. Huawei’s own roadmap says eight- and four-bit floats arrive with the 950 series: “Compared with the Ascend 910B and Ascend 910C, our newer chips – starting with the Ascend 950 chips – … will support more data formats, including FP32, HF32, FP16, BF16, FP8, MXFP8, HiF8, MXFP4, and HiF4.” So the FP8 and FP4 cells read not supported.

  1. CSET: Pushing the Limits, Huawei’s AI chip tests US export controls
  2. Epoch AI machine learning hardware database (ml_hardware.csv)
  3. Epoch AI: what did US export controls mean for China’s AI capabilities?
  4. SemiAnalysis: Nvidia’s new China AI chips circumvent US restrictions (public preamble only; the specification tables are behind the paywall)
  5. Federal Register, 13 October 2022: the rule that created ECCN 3A090 (govinfo PDF)
  6. Huawei Connect 2025 keynote: the Ascend roadmap
  7. Huawei Ascend: Atlas 800T A2 server spec table
  8. SemiAnalysis: Huawei AI CloudMatrix 384 (where 910B and 910C dies were made)

Ascend 910CHuawei (HiSilicon) · China

How the speed figures are measured. Derived from a system figure, with no vendor datasheet and no independent measurement. SemiAnalysis’s CloudMatrix 384 figure of 300 PFLOPS dense BF16 across 384 chips implies about 781 TFLOPS per chip. Epoch AI records 800. Huawei publishes no per-chip figure for the 910C. Its Atlas 900 A3 SuperPoD page gives 307.2, 288.7 or 240.3 PFLOPS FP16 across 384 chips, depending on the model, which is 800, 752 or 626 TFLOPS per chip. Huawei’s own roadmap says eight- and four-bit floats arrive with the 950 series: “Compared with the Ascend 910B and Ascend 910C, our newer chips – starting with the Ascend 950 chips – … will support more data formats, including FP32, HF32, FP16, BF16, FP8, MXFP8, HiF8, MXFP4, and HiF4.” So the FP8 and FP4 cells read not supported.

  1. SemiAnalysis: Huawei AI CloudMatrix 384
  2. MOFCOM spokesperson on the Unreliable Entity List measures naming TechInsights
  3. Epoch AI machine learning hardware database (ml_hardware.csv)
  4. Huawei Connect 2025 keynote: the Ascend roadmap
  5. Huawei Ascend: Atlas 900 A3 SuperPoD spec table

Ascend 950PRHuawei (HiSilicon) · China

How the speed figures are measured. From Huawei’s spec table for the Atlas 350 card, the shipping 950PR product. The table lists theoretical peaks of 425 TFLOPS FP16/BF16, 804 TFLOPS mxFP8/HiF8 and 1,561 TFLOPS mxFP4. Huawei’s 2025 roadmap gave the 950 die 1,000 TFLOPS FP8 and 2,000 FP4. Huawei's processor page gives the chip’s maximum configuration as 128 GB at 1.6 TB/s. The table uses the card’s figures throughout, because the card’s table is the only Huawei table that ties memory, compute and power together.

  1. Huawei Connect 2025 keynote: the Ascend roadmap
  2. Huawei: open-access SuperPoD architecture, including the Atlas 350 card on Ascend 950PR
  3. Huawei Ascend: Atlas 350 accelerator card spec table
  4. Huawei Ascend: Ascend 950PR processor page
  5. Huawei Ascend: Atlas 950 SuperPoD spec page

Ascend 950DTHuawei (HiSilicon) · China

How the speed figures are measured. From Huawei’s 950DT spec table, top speed grade: 547 TFLOPS FP16/BF16, 1,034 TFLOPS mxFP8 and 2,007 TFLOPS mxFP4. The table lists memory as 144 or 96 GB at 4 TB/s without tying either to a speed grade. Huawei’s 2025 roadmap had given the 950 die 1 PFLOPS FP8 and 2 PFLOPS MXFP4. Huawei’s Atlas 650E server carries 96 GB per chip, and its per-chip figures match the table’s lowest speed grade.

  1. Huawei Connect 2025 keynote: the Ascend roadmap
  2. Huawei Ascend: Ascend 950DT processor spec table
  3. Huawei Ascend: Atlas 950 SuperPoD spec page

Siyuan 590 (MLU590)Cambricon · China

How the speed figures are measured. Cambricon publishes no specifications for this part and has no product page for the Siyuan 590 on its site. No allowed source gives per-precision figures, and no document lists the data types the chip runs, so all three cells read not published.

  1. Cambricon corporate site
  2. Federal Register: Additions and Revisions to the Entity List, effective 16 December 2022 (adds the Cambricon entities)
  3. Epoch AI: AI chip sales methodology, chip price and cost estimates

MTT S5000Moore Threads · China

How the speed figures are measured. Moore Threads publishes no peak FLOPS for the MTT S5000. Its product page instead claims “full-precision compute support from FP8 to FP64” on the PH100 “Pinghu” chip. So FP16 and FP8 are supported, but no figures are published for them. Four-bit arithmetic falls outside the range Moore Threads claims, so the FP4 cell reads not supported. The page also claims at least 4,000 tokens per second of single-GPU prefill, at least 1,000 tokens per second of decode, and 95 percent linear scaling at 10,000-GPU cluster scale. No independent benchmark exists.

  1. Moore Threads MTT S5000 product page
  2. Moore Threads MTT KUAE cluster page
  3. Federal Register: Entity List Additions, 88 FR 71991, effective 17 October 2023 (adds the Moore Thread entities)
  4. Moore Threads: STAR Market IPO prospectus (Shanghai Stock Exchange, September 2025)