Glossary

The Code of Federal Regulations is the standing text of US rules, sorted into titles and parts. Title 15 holds the Export Administration Regulations. Part 734 says what is subject to them. Part 740 lists the license exceptions, and its supplement no. 5 lists the nineteen destinations eligible for License Exception AIA. Part 742 sets the licensing policy for each control.

A rule announced in the Federal Register stays in the CFR until it is removed, so the unenforced AI Diffusion rule still stands in the regulations.

Read it in Who Controls the ChainAlso in Memory and HBM

300 mm is the diameter of the standard wafer, about twelve inches. Older fabs run 200 mm, or 8-inch, wafers. The last increase in wafer size, to 300 mm, came in 2002.

Advanced chips start on 300 mm wafers. In SEMI's November 2020 World Fab Forecast, which CSET cited in January 2021, they carried 99.7 percent of world fab capacity at 45 nm and below.

Read it in Silicon and WafersAlso in Metrology and Inspection, Transistors and the Front End, Foundries and Fabs, Test and Assembly, The Economics of AI Chips

3A090 is the entry in the US export control list that covers advanced AI chips, defined by their total processing performance and performance density. Its part c, added in December 2024, covers high bandwidth memory. 4A090 covers the computers built from the chips. A chip that falls under 3A090.a needs a license for China. The AI Diffusion rule of January 2025 extended that requirement to every destination. But BIS says it enforces the requirement only for Country Groups D:1, D:4 and D:5 and for firms headquartered in D:5 or Macau.

It decides which AI chips need a license for China, so designers now build chips around its thresholds.

Read it in Who Controls the ChainAlso in Memory and HBM

3B001 is the main entry in the US export control list for chipmaking equipment. It is written as process specifications, such as an etch tool that cuts sideways or a deposition tool that coats holes more than 200 times deeper than they are wide. BIS created 3B090 in October 2022 and folded it into 3B001 and 3B002 in October 2023 (88 FR 73424). The related 3D and 3E entries cover the software and know-how that go with the tools.

It decides which chipmaking tools need an export license. It defines a tool by the process it can run, because the same chamber can add or remove material depending on its recipe.

Read it in Who Controls the ChainAlso in Chip Design, EDA and IP, Deposition and Etch

The insulating film inside the substrate, the small layered board that the chips in a high-end package sit on. The board is built up in layers, and a sheet of this epoxy film, about 10 micrometers thick, separates each layer of copper wiring from the next. The Japanese food company Ajinomoto first developed it in 1999.

Ajinomoto told investors in June 2026 that its film has held over 95 percent of its market since its launch. The company says practically all high-performance computers and servers rely on it.

Read it in Substrates and PCBs

A chip built to do the one kind of arithmetic machine learning needs, multiplying large grids of numbers, far faster than a general-purpose processor can. Nvidia's graphics processors, Google's Tensor Processing Units and Amazon's Trainium are all accelerators.

The whole supply chain exists to make accelerators, and export licenses are granted or refused for them.

In Chip Design, EDA and IP, Photomasks and Pellicles, Metrology and Inspection, Memory and HBM, Advanced Packaging, Test and Assembly, Systems and Networking, The Economics of AI Chips

The steps that assemble several finished chips into one component, sitting side by side or stacked, wired together closely enough to behave like a single larger chip. Ordinary packaging only puts one chip into a protective case with contacts on the bottom.

A modern AI accelerator needs more circuitry than a lithography machine can print in one exposure, and its memory must sit beside the logic, so it is assembled this way. Epoch AI found that TSMC's CoWoS packaging and the memory itself were the main limits on AI chip production in 2025.

Read it in Advanced PackagingAlso in Lithography, Metrology and Inspection, Memory and HBM, Test and Assembly, The Economics of AI Chips, Who Controls the Chain

The Affiliates Rule extended the Entity List to any company anywhere in the world that is at least half owned by a listed firm. The aim was to stop a listed company from buying through a subsidiary. It took effect on 29 September 2025 and was suspended for a year six weeks later.

It is suspended until 9 November 2026. If it returns, subsidiaries at least half owned by listed firms will again need licenses.

Read it in Who Controls the ChainAlso in Lithography, Deposition and Etch

The AI Diffusion rule, published on 15 January 2025, required a license to ship the most capable AI chips anywhere in the world. Its exceptions allowed unlimited shipments to nineteen destinations, capped volumes elsewhere and none to China. It also controlled the weights of frontier AI models.

Four months later BIS said it would not enforce the rule. But it withdrew none of the text, so the license requirement and exceptions still stand in the regulations. BIS says it enforces the requirement only for Country Groups D:1, D:4 and D:5 and for firms headquartered in D:5 or Macau.

Read it in Who Controls the Chain

A way of coating a chip a fraction of an atomic layer at a time. Each pulse of gas sticks to the surface and stops once the surface is covered. So the film comes out the same thickness on the floor and on the walls of a hole more than 50 times deeper than it is wide.

US regulators call atomic layer deposition an enabler of stacked memory and of FinFET and gate-all-around logic, and export rules name some of its tools directly. Chinese toolmakers held 2.6 percent of the market in 2025 on CSET's count, most of it from Piotech.

Read it in Deposition and Etch

ArF stands for argon fluoride, the gas mixture inside the laser that gives deep ultraviolet lithography its 193-nanometer light. Scanners, the machines that print each layer, use this light in two ways. A dry scanner shines it through air, and an immersion scanner through a thin film of water between lens and wafer, which prints finer lines. ArF scanners print most of the fine layers on any chip made without extreme ultraviolet.

ArF immersion scanners made up 42 percent of ASML's system sales in 2025. They are also the kind that a Chinese state-owned firm was reported in July 2026 to be producing at home.

Read it in LithographyAlso in Chemicals, Gases and Photoresist

A chip designed for one company's own workload and not sold on the open market. Google's Tensor Processing Unit and Amazon's Trainium are chips of this kind. An Nvidia part sold to any customer is not.

A custom chip is tuned to one company's workload, but a chip sold to everyone comes with mature software and a resale market. Design houses such as Broadcom and Marvell turn the buyer's design into silicon and sell the finished chips to the buyer.

Read it in Chip Design, EDA and IPAlso in Systems and Networking

Automated test equipment, or ATE, is the machine that connects to a chip, on the wafer or in its package, feeds it test patterns and checks whether the answers coming back are right. Advantest's July 2026 investor guide counts test as the only manufacturing step that puts electrical signals through the chip.

An AI accelerator joins a dozen expensive pieces, and one bad piece scraps them all. So each die is tested before assembly. Advantest's April 2025 investor guide put Advantest and Teradyne at about 80 percent of the tester market.

Read it in Test and Assembly

Inside a fab, the back end of line is the second half of making a chip, the dozen or more layers of copper wiring stacked above the transistors. In the industry at large, the back end means everything after the wafer leaves the fab: grinding, dicing, packaging and test.

Wiring is now as hard to make as the transistor. Among the firms that package and test chips after they leave the fab, four of the ten largest by 2024 revenue are headquartered in China, in a TrendForce ranking cited by CSET.

Read it in Transistors and the Front EndAlso in Advanced Packaging, Test and Assembly

Backside power delivery moves a chip's power wiring to the underside of the wafer, so the wiring above the transistors carries only signals. After the transistors and signal wiring are built, the wafer is bonded face down to a second wafer and ground thin, and the power wires are built on its back. Power arrives through tiny holes etched up from below, clear of the crowded top.

It is one of the few remaining ways to make a chip faster without shrinking the transistor. Intel ships it on its 18A process. TSMC says A16, its first process with it, will be production-ready in the second half of 2026.

Read it in Transistors and the Front EndAlso in Deposition and Etch

The base die is the bottom chip of an HBM stack, the one that manages the memory dies above it and talks to the processor on their behalf. For HBM4, SK hynix moved it to TSMC's advanced logic process so it can hold more functions. Samsung's HBM4, shipped from February 2026, uses a 4 nm logic base die.

SK hynix made its own base dies up to HBM3E, so the move gives TSMC a role inside a product it does not make.

Read it in Memory and HBMAlso in Advanced Packaging

A baseboard is the large circuit board that eight accelerator modules bolt onto inside a server. It carries their power and the links between them. On Nvidia's baseboard, switch chips let any two modules reach each other at full speed. Nvidia's module is called SXM and its baseboard HGX. The open-standard equivalents are OAM and UBB.

With an eight-module baseboard, the eight accelerators in one server work as one unit. Rack-scale systems such as the NVL72 drop the baseboard and join 72 GPUs through switch trays in the rack.

Read it in Systems and Networking

A way of joining a packaged chip to a circuit board using a grid of small solder balls across the underside in place of a row of pins around the edge. Heating the assembly melts every ball at once into a permanent joint.

The number and spacing of those balls limit how much current and how many signals can reach a package.

Read it in Substrates and PCBs

The Big Fund is the nickname for China's National Integrated Circuit Industry Investment Fund, the state vehicle that puts government money into Chinese chip firms. Its third round, raised in May 2024, came to 344 billion yuan, about $47 billion.

CSIS puts China's cumulative state funding for chips since 2014 at an estimated $150 billion. The money has built a domestic tool industry but no leading-edge node.

Read it in Who Controls the ChainAlso in Transistors and the Front End

The itemized list of every purchased part in a finished product and what each part cost, the way a builder's invoice prices lumber, wiring and fixtures separately.

A bill of materials shows which suppliers get the money a buyer spends. Epoch AI estimated in December 2025 that memory made up about half of the roughly $6,400 manufacturing cost of an Nvidia B200.

Read it in The Economics of AI Chips

The US government office that decides which technologies may be exported, to whom, and on what conditions. It writes the rules, issues the licenses and brings the enforcement cases.

BIS wrote the US restrictions on selling AI chips and chipmaking tools to China in a series of rules. It can change a threshold by publishing a notice in the Federal Register, with no act of Congress needed.

Read it in Who Controls the ChainAlso in Chip Design, EDA and IP, Lithography, Deposition and Etch, Metrology and Inspection, Memory and HBM

Burn-in runs a chip hot and at raised voltage for minutes to days, so that any part that would fail early fails in the factory before it is shipped. It can run on the wafer or in the package. Aehr, a maker of burn-in systems, says its lead AI customer is moving all burn-in for its accelerators from the system level to the wafer.

One weak die in a package of a dozen expensive parts scraps all of them, so burn-in on the wafer protects everything else in the package.

Read it in Test and Assembly

A busbar is a thick bar of solid copper that carries large currents down the back of a rack to the boards that need them. An ordinary cable carrying the same current would overheat. At the 54 volts used inside racks such as the GB300 NVL72, a one-megawatt rack would need up to 200 kilograms of busbar, by Nvidia's estimate.

Nvidia is moving its racks to 800 volts, which cuts the current, so a megawatt rack will not need bars that heavy.

Read it in Data Centers and Power

Money a company spends on long-lived physical assets such as buildings, machines and servers, as distinct from salaries and other running costs.

The largest cloud companies' capex pays for the chips, racks and buildings of the AI buildout. Alphabet, Amazon, Meta, Microsoft and Oracle spent $448.2 billion of capital in 2025, the sum of Epoch AI's quarterly figures. Epoch AI says they will spend $770 billion in 2026 if the trend continues.

Read it in Data Centers and PowerAlso in Substrates and PCBs, The Economics of AI Chips

Case-by-case review means a license is required and each application is judged on its own, with no presumption either way. Since January 2026 Nvidia's H200 and AMD's MI325X have been reviewed this way for China, with conditions attached to each approval.

It is the middle ground between an open market and a presumption of denial. In early 2026 the United States settled on it for chips such as the H200 bound for China.

Read it in Who Controls the Chain

A chip is a small rectangle of silicon, usually smaller than a fingernail, that carries a complete electronic circuit, often made of billions of transistors. It is cut from a wafer after the circuit has been built up on it layer by layer.

The supply chain is every firm and country that takes part in making chips, and some of them can stop production.

Read it in Silicon and WafersAlso in Chip Design, EDA and IP, Chemicals, Gases and Photoresist, Lithography, Photomasks and Pellicles, Deposition and Etch, Metrology and Inspection, Transistors and the Front End, Foundries and Fabs, Memory and HBM, Advanced Packaging, Substrates and PCBs, Test and Assembly, Systems and Networking, Data Centers and Power, The Economics of AI Chips, Who Controls the Chain

One of several smaller pieces that a chip has been deliberately split into, each manufactured separately and then wired back together inside a single package. A chip built this way is like a house assembled from prefabricated rooms.

Many large accelerators need more circuitry than a lithography machine can print in one exposure, so they are built from chiplets. That makes packaging, the step that joins the chiplets, the hard part. Epoch AI found that TSMC's CoWoS packaging and memory were the main limits on AI chip production in 2025.

Read it in Chip Design, EDA and IP

The CHIPS and Science Act authorized about $52.7 billion of US federal money for the chip industry. By July 2025 the Commerce Department had awarded $30.9 billion of direct funding to 19 companies for 40 projects.

Its grants paid a median 14.2 percent of each funded project's capital cost. In August 2025, $5.7 billion of grants awarded to Intel but not yet paid went into the government's $8.9 billion purchase of a 9.9 percent stake in Intel.

Read it in Who Controls the ChainAlso in Silicon and Wafers, Foundries and Fabs, Advanced Packaging

A step in the supply chain where so few firms or countries can do the work that losing one of them stops everybody.

One sanction or one factory fire at a chokepoint reaches the whole industry, and so does a government policy aimed at one.

In Deposition and Etch, Advanced Packaging, Who Controls the Chain

CMOS, short for complementary metal-oxide-semiconductor, is the standard way of building digital circuits from pairs of transistors. Each n-type transistor, which switches on when the voltage on its gate is high, is matched with a p-type transistor, which switches on when that voltage is low. In either logic state one side of the circuit is off, so little current flows except while it switches.

CMOS became the dominant technology for making chips because its circuits drew close to zero power while idle, which kept heat in check as chips packed in more transistors. FinFET and gate-all-around transistors are newer shapes for the same n-type and p-type pairs.

Read it in Transistors and the Front End

Chemical mechanical polishing, or CMP, rubs a wafer's surface flat again after each new layer goes on, using a pad and a liquid full of fine grit called slurry. Without it the next layer would be printed on a surface too bumpy to focus on.

Japanese companies held 51 percent of polishing-slurry sales in 2023, counted by company nationality. CSET's January 2021 brief, drawing on 2019 market reports, put DuPont and Cabot Microelectronics at about 56 percent of a $790 million slurry market. Cabot was renamed CMC Materials in October 2020, and Entegris bought it in July 2022. DuPont's electronics business became Qnity Electronics in November 2025.

Read it in Chemicals, Gases and PhotoresistAlso in Photomasks and Pellicles, Advanced Packaging

Co-packaged optics puts the parts that turn electrical signals into light and back onto the switch chip's own package instead of into plug-in modules at the front of the box. Broadcom keeps the lasers that supply the light in separate modules that can be replaced in the field.

Broadcom and Nvidia are moving the optics onto the switch package partly to cut the power the optics use. Broadcom says its Tomahawk 6 Davisson cuts optical interconnect power by 70 percent.

Read it in Systems and NetworkingAlso in Memory and HBM

A coater/developer, or track, is the machine that spins a thin coat of photoresist onto the wafer before it enters the scanner. After the wafer comes out, the same machine washes away the exposed parts, so every printed layer passes through it twice.

No pattern can be printed without it. Tokyo Electron's own results put its share of the market at 91 percent in 2025.

Read it in Deposition and Etch

The coefficient of thermal expansion is how much a material expands for each degree it warms. Silicon barely expands and epoxy expands more, so when the two are bonded and heated, the package bends.

Warpage control, keeping a package from bending, means matching expansion across die, bridge, interposer and substrate. It gets harder as packages grow.

Read it in Substrates and PCBsAlso in Photomasks and Pellicles

A limit set on the amount of arithmetic used to train an AI model. It counts operations, whichever chips run them. The AI Diffusion rule of January 2025 made one an export control. ECCN 4E091 covers "'Parameters' for an artificial intelligence model trained utilizing 10^26 or more 'operations'". The rules require a license to send such parameters to every destination worldwide (15 CFR 742.6(a)(13)). Article 51(2) of the EU AI Act sets Europe's line ten times lower. It presumes a model has high-impact capabilities when the cumulative computation used for training is "greater than 10^25" floating point operations.

Every other control threshold measures a chip, but this one measures the model the chips train. Article 51(3) of the AI Act lets the European Commission change the EU figure by delegated act. Such an act takes effect unless the European Parliament or the Council objects within three months (Article 97(6)). BIS said in May 2025 that it would not enforce the AI Diffusion rule, but 4E091 still stands in the regulations.

Read it in Who Controls the Chain

A four-band judgment of how many firms could credibly supply a stage today, taken at the narrowest step inside it. Extreme means three or fewer, or one firm holding more than half the stage. High means four to six, with the top two taking most of the revenue. Moderate means seven or more, none of them dominant. Low means many, with the scarce input something another industry sells at volume. Where a figure exists for the top country's share of the segment, it is a second check. When the two disagree, the supplier count wins.

The fewer the firms that can do a stage, the more one accident or one license decision affects the whole chain.

In Who Controls the Chain

The consignee is the party a shipment is sent to, the name on the export license. A named consignee, such as G42 in the United Arab Emirates, can receive controlled chips on the terms attached to its own name.

The July 2026 UAE rule names the Emirati government, G42 and eight US-headquartered AI companies as consignees who can take controlled AI chips without a license. The license-free treatment is tied to those named buyers.

Read it in Who Controls the Chain

The groups that US export rules sort the world's countries into, published as supplement no. 1 to 15 CFR part 740. A:5 and A:6 list close partners. D:1, D:4 and D:5 are the national security, missile technology and arms-embargoed groups. E:1 and E:2 are the most restricted. A country can be in several groups at once, and the license requirement usually depends on which.

US license rules for AI chips are written in terms of these groups. Chips in the 3A090.b band, the band below the top one, need a license for D:1, D:4 and D:5 destinations not also in A:5 or A:6 (15 CFR 742.6(a)(6)(iii)(B)). The UAE moved from D:3 and D:4 into A:5 in July 2026. But the rule names the UAE, so these chips still need a license there, except for approved Emirati consignees (15 CFR 742.6(a)(6)(iii)(B)).

Read it in Who Controls the ChainAlso in Metrology and Inspection, Memory and HBM

TSMC's method for mounting logic chips and memory stacks side by side on a shared interposer, a layer of fine wiring, then mounting that interposer on a rigid base board. In CoWoS-S the interposer is one piece of silicon. In CoWoS-L, used for Nvidia's Blackwell and Rubin, it is layers of fine copper wiring with small embedded silicon bridges. Nearly every high-end AI accelerator is built this way.

Epoch AI found that TSMC's CoWoS packaging and memory were the main limits on AI chip production in 2025. It estimates that Nvidia used 60.3 percent of all CoWoS that year. SemiAnalysis judged in March 2026 that CoWoS supply was easing, but in July 2026 TSMC said its packaging capacity was so tight that it limited customers' growth.

Read it in Advanced PackagingAlso in Foundries and Fabs, Substrates and PCBs, Test and Assembly, The Economics of AI Chips, Who Controls the Chain

The critical dimension is the width of the finest printed feature on a layer. A CD-SEM is an electron microscope built to measure it across a wafer without cutting anything.

Fabs measure it to tell whether each lithography and etch step came out the right width. In 2025 Hitachi held 71.9 percent of the market for the tools that measure it, by CSET's count. They are the one kind of inspection or measurement tool that Japan leads.

Read it in Metrology and Inspection

CSIS, the Center for Strategic and International Studies, is a bipartisan, nonprofit policy research organization in Washington, D.C., founded in 1962. Its technology researchers publish assessments of China's chipmaking and of US export controls.

Its reports judge how far Chinese chipmakers are from replacing foreign tools. In September 2025 CSIS judged that extreme ultraviolet machines remained firmly out of China's reach despite massive state investment, including $43 billion that China announced for developing its own.

Read it in LithographyAlso in Chip Design, EDA and IP, Transistors and the Front End, Memory and HBM, Who Controls the Chain

Chemical vapor deposition, or CVD, grows a film by flowing gases over a hot wafer so they react on its surface and leave a solid layer behind. The plasma-enhanced version, PECVD, runs cooler. The gases used are called precursors.

CVD made up $11.2 billion of a $26.2 billion deposition tool market in 2025, most of it the plasma-enhanced kind. Chinese toolmakers' share of the deposition tool market rose from 2 to 7 percent between 2019 and 2024.

Read it in Deposition and Etch

The share of controlled American content a foreign-made item may contain before US export rules, the EAR, apply to it. Under 15 CFR 734.4 the general threshold is 25 percent of the item's value, and 10 percent for the most restricted destinations. Above the threshold the item falls under the EAR, and below it the item does not.

It decides whether foreign-made goods with some US content fall under American rules. The foreign direct product rules work differently and catch an item whatever its share of US content. Under 15 CFR 734.4(a)(3), equipment in ECCN 3B993.f.1 has no de minimis level when it is bound for advanced-node chip production. The exception is equipment first exported from a country that also controls it.

Read it in Who Controls the Chain

The average number of chip-killing flaws per square centimeter of processed wafer. It is a fab's quality score, inferred from how many chips come out working.

AI accelerators have some of the largest dies in production, and yield, the share of dies that work, falls steeply as die area times defect density grows. In a textbook example at 0.8 defects per square centimeter, 49.2 percent of dies 1 centimeter on a side come out flawless, against 11.3 percent of dies 2 centimeters on a side. The share that can be sold is higher on chips that carry spare blocks.

Read it in Metrology and Inspection

An order from BIS that shuts a named party out of trade in US-controlled items, as a sanction or a protective measure, with no license policy involved. Under 15 CFR 764.3 it restricts the party's exports, reexports and in-country transfers of items subject to the EAR, and its access to them. It can also suspend or revoke the party's outstanding licenses. There is no application to file. Orders can be issued outright or suspended and later activated.

It can cut a named party off from every item subject to the EAR. The order activated against ZTE in April 2018 stayed in force until BIS terminated it 89 days later as part of a settlement (83 FR 17644; 83 FR 34825).

Read it in Who Controls the Chain

Adding a layer of material to a wafer. Machines knock atoms off a solid target so they land on the surface, react gases at the surface so a film grows there, or plate metal out of a liquid. It is how the insulators, the wires and the parts of each transistor are built up.

Making one chip takes 1,000 to 1,500 steps by a 2025 industry estimate, and many of them are deposition and etch. AI hardware needs films that reach the bottom of deeper holes. Four firms make most of the tools, but deposition is among the tool types where Chinese makers gained the most share between 2019 and 2024.

Read it in Deposition and EtchAlso in Chemicals, Gases and Photoresist, Lithography, Metrology and Inspection, Transistors and the Front End, Advanced Packaging, Who Controls the Chain

Dicing cuts a finished wafer into its individual dies with a diamond saw or a laser. Grinding, done first, thins the wafer from the back, and for stacked memory it goes on until the copper columns inside the dies come through.

Stacked high bandwidth memory (HBM) depends on that grinding. Disco of Japan held 87 percent of the world market for dicing saws and wafer grinders in 2025, by CSET's count.

Read it in Test and AssemblyAlso in Advanced Packaging

One rectangular chip cut out of a wafer. Hundreds are printed side by side on the same disc and then sliced apart, and each separated rectangle is a die.

Cost and yield are counted per die. A GPU die that fills the largest area one exposure can print loses far more silicon to one fatal defect than a small chip does.

Read it in Silicon and WafersAlso in Chip Design, EDA and IP, Metrology and Inspection, Transistors and the Front End, Memory and HBM, Advanced Packaging, Test and Assembly, The Economics of AI Chips

A dielectric is an insulator: a material that does not conduct, such as the glassy oxides and nitrides between a chip's wires or the epoxy in a package substrate. Dielectric etch cuts holes and trenches through those insulating layers so the wires can be laid in.

How much signal a dielectric absorbs sets how fast a substrate or circuit board can run. So the suppliers of laminates, the insulating sheets these boards are made from, matter to AI systems.

Read it in Deposition and EtchAlso in Advanced Packaging, Substrates and PCBs

A computer's main working memory. Each bit is a charge held in a microscopic capacitor that leaks, so the chip has to refresh its contents constantly. It forgets everything when the power goes off.

HBM is a stack of DRAM chips, and the three leading DRAM makers, SK hynix, Samsung and Micron, make nearly all of it. SK hynix says the shift of production capacity to HBM left ordinary DRAM, the kind in PCs and phones, undersupplied. The company says the shortage helped drive a significant price recovery from the third quarter of 2025.

Read it in Memory and HBMAlso in Deposition and Etch, Metrology and Inspection, Who Controls the Chain

Chipmaking light from gas lasers, at 248 or 193 nanometers, and the machines that print with it, which still make up most lithography tools. Filling the gap between lens and wafer with water sharpens the image, a method called immersion.

A fab without extreme ultraviolet machines can reach leading-edge logic only with immersion deep ultraviolet and several passes per layer, as SMIC does. So Dutch export licensing covers the most advanced immersion tools.

Read it in LithographyAlso in Photomasks and Pellicles, Transistors and the Front End, Foundries and Fabs, Who Controls the Chain

The body of US rules that governs the export of commercial goods, software and technology, including items with both civilian and military uses. The Bureau of Industry and Security writes and enforces them. They run from 15 CFR part 730 to part 774. Part 734 sets what they cover, part 742 the license requirements, part 744 the end-use and end-user controls, part 740 the exceptions and part 764 the penalties.

American export rules on chips and chipmaking tools are amendments to these regulations, made by notice in the Federal Register with no act of Congress.

Read it in Who Controls the Chain

The label for an item that falls under US export rules but is not named on the Commerce Control List, the catalog of controlled items. The label is defined at 15 CFR 734.3(c). It is a catch-all category, but an EAR99 item still needs a license if it is going to a listed party or a controlled end use.

An EAR99 item can usually ship without a license, but a listed buyer, a controlled end use or an embargoed destination can still require one. So exporters of unlisted items have to follow the end-user controls in part 744 of the EAR too.

Read it in Who Controls the Chain

The catalog number that US export rules assign to a controlled item, similar to a customs tariff code but for security-sensitive technology. Number 3A090 covers advanced computing chips and 3B001 covers chipmaking equipment.

An item's classification number determines whether it needs a license. So the technical thresholds written into each number set which products are controlled.

Read it in Who Controls the ChainAlso in Deposition and Etch, Memory and HBM

The software that turns a description of what a chip should do into the exact pattern of shapes to be printed on silicon. It also proves the design will work before anyone commits money to masks and wafers.

Three vendors sell the only software that covers every step of designing a leading-edge chip. Since October 2022 software made for designing chips with gate-all-around transistors has needed a US export license. In May 2025 the US government sent letters to the three vendors requiring a license for all their sales to China, and it lifted the requirement on 2 July.

Read it in Chip Design, EDA and IP

An electron beam is a stream of electrons focused to a spot far smaller than any spot of light. Mask shops use it to write the pattern onto a photomask, and fabs use it to inspect wafers for defects light cannot see and to measure line widths. A multi-beam tool fires many beams at once, because a single beam is slow.

In 2023 Intel called Austria's IMS Nanofabrication the established leader in the multi-beam writers that advanced EUV masks require. Since December 2024 US rules have controlled wafer inspection tools that use two or more beams to find defects 21 nm across or smaller.

Read it in Photomasks and PelliclesAlso in Metrology and Inspection

Electronic-grade, or semiconductor-grade, silicon is refined until its metal impurities are no more than a few parts per billion, pure enough for chips. Solar-grade silicon is a less pure grade made for solar cells.

Every chip starts from it. The Commerce Department found in 2026 that semiconductor-grade polysilicon makes up only 2.4 percent of global production. The German wafer maker Siltronic names five major suppliers for 2025: Wacker, Hemlock, OCI, Tokuyama and Mitsubishi. None of them is Chinese.

Read it in Silicon and WafersAlso in Chemicals, Gases and Photoresist

EMEA stands for Europe, the Middle East and Africa, one region in the breakdowns that companies publish of where their sales go.

ASML is based in the Netherlands, yet tools shipped to EMEA made up 1 percent of its net system sales in 2025, against 33 percent for China.

Read it in Lithography

Export rules that depend on who the buyer is and what they will do with the item, whatever the item is. The same tool can ship freely to one customer and need a license that will be refused for another.

A company can lose access to US-controlled items because of who owns it or what its site produces. In September 2025 US rules were extended to firms at least 50 percent owned by listed entities, though the extension is suspended until 9 November 2026.

Read it in Who Controls the ChainAlso in Chip Design, EDA and IP, Chemicals, Gases and Photoresist, Deposition and Etch

A published list of foreign companies, institutes and individuals. Anyone anywhere, American or foreign, needs a license to send them an item subject to the EAR. Each entry states its own license review policy. Most carry a presumption of denial, meaning the license will normally be refused. SMIC's entry, as amended in December 2024, is a presumption of denial for all items. The exception is tools designed for 200 mm wafer production and bound for a 200 mm plant, which are reviewed case by case. The list is supplement no. 4 to 15 CFR part 744, and the license requirement is in 15 CFR 744.11.

It names an organization, so it is one of the simplest tools the US government has. In September 2025 the US extended each listing to companies at least 50 percent owned by listed firms, but that extension is suspended until 9 November 2026 (90 FR 50857).

Read it in Who Controls the ChainAlso in Lithography, Deposition and Etch

Epitaxy grows a fresh layer of crystal on top of a wafer, atom by atom, so the new layer continues the crystal beneath it with almost no flaws. An epitaxial wafer is a plain wafer with that extra layer, and the transistors are built in it.

Flaws in that layer can make the transistors leak current. The industry association SEMI credits the 2025 rise in wafer shipments to AI demand for advanced epitaxial wafers for logic chips and polished wafers for high-bandwidth memory.

Read it in Silicon and WafersAlso in Deposition and Etch, Transistors and the Front End

Removing material from a wafer wherever the printed pattern says it should not be. Most etch tools turn a gas into a plasma whose ions and fragments eat one material and leave the material beside it alone.

Wrap-around transistors need etch that cuts sideways while sparing the material beside it. Stacked memory needs holes far deeper than they are wide. So US rules control etch tools by selectivity, meaning how well a tool cuts one material while sparing another, and by hole shape.

Read it in Deposition and EtchAlso in Chemicals, Gases and Photoresist, Lithography, Photomasks and Pellicles, Metrology and Inspection, Transistors and the Front End, Memory and HBM, Advanced Packaging, Who Controls the Chain

Ethernet is the ordinary networking standard of offices and the internet, now made fast and reliable enough to link the servers of an AI cluster. Its switch chips, such as Broadcom's Tomahawk, route traffic between thousands of accelerators.

Broadcom has doubled the bandwidth of its Ethernet switch chips every generation, from 25.6 Tbps on one chip in Tomahawk 4 in 2019 to 102.4 in Tomahawk 6 in 2025.

Read it in Systems and NetworkingAlso in Chip Design, EDA and IP

The light that prints the finest layers of every leading-edge chip, and the machines that print with it. Its wavelength is 13.5 nanometers, and shorter light draws finer lines. Air and glass both absorb it, so the machine works in a vacuum and carries the light on mirrors. The light comes from droplets of molten tin, 50,000 a second, each hit twice by a laser.

The finest layers set how densely transistors and wires pack, so the most advanced AI chips depend on EUV. Only ASML makes the machines, and export controls block it from shipping them to Chinese chipmakers.

Read it in LithographyAlso in Chemicals, Gases and Photoresist, Photomasks and Pellicles, Metrology and Inspection, Transistors and the Front End, Foundries and Fabs, Who Controls the Chain

An export control is a rule that requires the government's permission for a sale. The government names an item and a country or a buyer. From then on its own companies must hold a license before they ship that item to that country or buyer. The United States extends some of these rules to goods made abroad with American technology.

It works only when the controlling country's firms make something the buyer cannot get elsewhere.

Read it in Who Controls the ChainAlso in Chip Design, EDA and IP, Chemicals, Gases and Photoresist, Lithography, Deposition and Etch, Metrology and Inspection, Memory and HBM, Systems and Networking

The factory where wafers are processed into chips. It is a cleanroom where each wafer moves from machine to machine in a sealed pod for months. The building costs tens of billions of dollars.

In 2023 BCG estimated that a new 2 nm-class fab finished in 2026 would cost $35 to $43 billion to own over ten years. SemiAnalysis judged in December 2025 that finding enough workers remained a major challenge for TSMC in Arizona. TSMC has yet to build one of its largest fabs outside Taiwan.

Read it in Foundries and FabsAlso in Silicon and Wafers, Chemicals, Gases and Photoresist, Lithography, Photomasks and Pellicles, Deposition and Etch, Metrology and Inspection, Transistors and the Front End, Advanced Packaging, Data Centers and Power, Who Controls the Chain

A chip company that designs and sells chips but owns no factory, paying a contract manufacturer, a foundry, to make them. Nvidia, AMD, Apple, Qualcomm and Broadcom all work this way.

The fabless model concentrates manufacturing in a handful of foundries. So a designer's supply, its costs and where its chips are made all depend on a company it does not control.

Read it in Foundries and Fabs

The Federal Register is the US government's daily journal, where every new rule is published. An export rule can take effect a few days before it is printed there, as the UAE rule did in July 2026. A citation such as 89 FR 96790 means volume 89, page 96790, and is the usual way to cite a rule.

US export rules change by notices published there, with no act of Congress needed.

Read it in Who Controls the ChainAlso in Memory and HBM

A transistor whose channel, the strip that current flows through, stands on edge like a shark fin. The gate, the electrode that switches the current, wraps around three sides of the fin instead of resting on one. More contact means firmer control and less leakage when the switch is meant to be off.

TSMC's leading-edge processes used FinFETs until N2, its first process with gate-all-around transistors, entered volume production in late 2025. The October 2022 US rules used FinFET or 16/14 nm logic as one of their thresholds for an advanced fab.

Read it in Transistors and the Front EndAlso in Deposition and Etch

A count of how many arithmetic operations on floating-point numbers, numbers with a fractional part, a chip can perform each second, the way horsepower counts an engine's output.

It is the standard unit of AI compute, but two chips' figures can be compared only when the number format behind each, such as 8-bit or 16-bit, is stated. US export rules use their own score, TPP, which weights each operation by its bit length.

A US rule that puts a foreign-made item under American control when two tests are both met. The first is about the product: the item was made directly from specified US technology or software, or in a plant that was. The second is about the destination: the item is going somewhere, or to someone, the rule names. The mechanics are in 15 CFR 734.9.

The rule lets US controls reach goods made outside the United States. Without it, a buyer on the Entity List could escape US controls by ordering chips from a supplier outside the United States. With it, a chip made in Taiwan on American tools for Huawei needs a US license. For listed firms the rule reaches only those whose entry carries a footnote naming it, such as Huawei's (15 CFR 734.9(e)).

Read it in Who Controls the ChainAlso in Deposition and Etch, Metrology and Inspection, Memory and HBM

A company, or a division of one, that manufactures chips designed by other companies. A pure-play foundry, the model TSMC pioneered after its founding in 1987, makes no products of its own. The model works because no chip company sells enough of one product to fill a modern fab on its own.

All six of TSMC's largest plants are in Taiwan. Taiwan held 69 percent of the world's logic capacity below 10 nm in 2022, so political events there affect the whole chip supply.

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Ways of writing a number using only 8 or 4 binary digits, or bits, far fewer than standard formats use. Each number is less precise, but the chip can perform and store far more of them. That trade-off suits machine learning, which can work with less exact numbers.

Lower precision raises a chip's headline speed, so a performance figure quoted without its number format cannot be compared. US export rules allow for this by weighting each operation by its bit length.

The front end of line is the first half of making a chip, the steps that build the transistors in the silicon. In the industry at large, the front end means the whole wafer fab, as against the back end where chips are packaged and tested.

SemiAnalysis judged in March 2026 that front-end capacity had overtaken packaging as the main bottleneck on AI chip output. But TSMC said in July 2026 that its packaging capacity still limited customers' growth.

Read it in Transistors and the Front EndAlso in Advanced Packaging

Gallium and germanium are metals used in electronics. Gallium goes into compound chips such as radio parts, LEDs and lasers, and germanium into fiber optics, infrared optics, semiconductors and solar cells. Both are recovered as byproducts, gallium from processing bauxite and germanium from certain zinc ores and coal.

The US Geological Survey put China's share of world production of primary low-purity gallium at 99 percent in February 2026. China has required licenses to export both metals since August 2023. Its December 2024 ban on exports of both to the United States is suspended until 27 November 2026.

Read it in Chemicals, Gases and Photoresist

A transistor in which the gate, the electrode that switches the current, wraps all the way around the channel that current flows through. In a FinFET, the design it replaces, the gate touches three sides. Surrounding the channel gives the gate firmer control than a fin allows, so less current leaks when the switch is off.

Only TSMC, Intel and Samsung make it in volume. It needs etch that cuts sideways, which US export rules control. Customers building 2 nm gate-all-around capacity lifted ASM International, the leader in atomic layer deposition, to record revenue in 2025.

Read it in Transistors and the Front EndAlso in Chip Design, EDA and IP, Deposition and Etch, Who Controls the Chain

GB/s is gigabytes per second, the measure of how much data a link or a memory can move. TB/s is a thousand times more. A lowercase b, as in Gb/s or Tbps, counts bits, each an eighth of a byte. One HBM4 stack moves over 2 TB/s. NVLink 6 gives each GPU 3,600 GB/s, according to Nvidia's January 2026 Rubin launch.

The October 2022 US rule caught chips with a processing score of 4,800 or more and an input and output rate of 600 GB/s or more (87 FR 62186). Since January 2026, chips with total DRAM bandwidth below 6,500 GB/s and a processing score, or TPP, below 21,000 can be licensed case by case for China (91 FR 1684).

Read it in Memory and HBMAlso in Advanced Packaging, Systems and Networking

Glass cloth is a woven fabric of fine glass fibers that gives a substrate core or circuit board its stiffness. T-glass is a special grade that barely expands when heated, which helps keep a large package flat.

Nitto Boseki of Japan claims an overwhelming advantage in low-expansion glass cloth. It says demand seems to have risen about two to three times since its fiscal 2024 to 2027 plan was set.

Read it in Substrates and PCBsAlso in Systems and Networking

A processor originally built to draw video game images by doing thousands of simple calculations at once. Neural networks turned out to need the same kind of arithmetic, so the GPU became the default AI processor.

Nvidia used 60.3 percent of all CoWoS packaging in 2025, on Epoch AI's estimate. The US required a license for Nvidia's H20 in April 2025. Since January 2026 it has reviewed applications to sell the H200 to buyers in China case by case.

In Chip Design, EDA and IP, Silicon and Wafers, Transistors and the Front End, Memory and HBM, Substrates and PCBs, Systems and Networking, Data Centers and Power, The Economics of AI Chips

The share of a sale left over after paying what it cost to make the thing, before research, sales and overheads are counted. A 70 percent gross margin means $70 of every $100 of revenue is left after manufacturing cost.

Gross margin shows which firms have pricing power. In quarters ending June to September 2026, Micron's was 86.8 percent and Nvidia's 75.0 percent. The assembly and test houses Amkor and ASE were at 16.8 to 27.3 percent, counting ASE's packaging and test segment alone.

Read it in The Economics of AI ChipsAlso in Lithography, Foundries and Fabs

Stacked memory built for AI chips. Up to sixteen memory chips are stacked into a cube and wired together through copper-filled holes made in each chip before stacking. The cube sits a few millimeters from the processor. It holds the model the chip is running, the numbers called weights, and hands them to the processor over 1,024 or more wires at once.

To write each word of an answer, the chip reads the whole model from this memory, along with the record of the conversation so far. A larger model or a longer conversation needs more memory, so the size and speed of HBM usually set how many people one chip can serve. HBM is the largest line in the bill of materials of an Nvidia B200. SK hynix, Samsung and Micron make nearly all of it.

Read it in Memory and HBMAlso in Chip Design, EDA and IP, Silicon and Wafers, Deposition and Etch, Metrology and Inspection, Transistors and the Front End, Foundries and Fabs, Advanced Packaging, Test and Assembly, The Economics of AI Chips, Who Controls the Chain

The next generation of extreme ultraviolet machine, whose larger mirrors collect light over a wider angle and so print smaller features. The wider optics also halve the area the machine can print in one exposure, so a large chip has to be stitched together from two exposures.

It cuts the smallest printable feature from 13 nanometers to 8, and TSMC expects more AI chip layers to need it. Each machine sells for an estimated $350 to $400 million. Intel says it uses High-NA in volume production for select layers of some 18A products. TSMC plans to use it in high-volume manufacturing from 2030.

Read it in LithographyAlso in Photomasks and Pellicles, Foundries and Fabs

High-performance computing is the industry's name for the heavy end of the market: supercomputers, AI accelerators and the server processors beside them. A foundry's HPC platform is the version of a node tuned for those chips.

AI accelerators are part of this segment and need package substrates with more layers than earlier HPC chips. Ajinomoto, which makes the insulating film between those layers, counts 11 layers of it on each side of the core in a 2026 AI package substrate, against nine on each side of an HPC substrate around 2023.

Read it in Foundries and FabsAlso in Metrology and Inspection, Substrates and PCBs

High-volume manufacturing is the point where a new process or product stops being a trial and is made in volume for sale. Output then climbs to full rate during the ramp.

Foundries announce the date a process reaches it, and before then the process runs only in trials such as risk production.

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Joining two chips by bonding their copper pads, and the glass-like insulator around them, directly to each other, with no solder in between. Removing the solder lets connections be packed much more tightly and shortens the path heat has to travel out.

An SK hynix tech note puts microbumps about 20 micrometers apart and hybrid-bonded pads under 1 micrometer apart. It expects full-scale use in HBM at HBM4E or HBM5, where stacks are projected to pass twenty layers.

Read it in Advanced PackagingAlso in Test and Assembly

Hydrogen fluoride is a gas that dissolves glass, and hydrofluoric acid is its solution in water. Fabs use both to strip oxide layers and clean wafers between steps. Like other cleaning chemicals, it is purified until metal impurities are down to parts per trillion.

When Japan put it under individual export licenses for South Korea in 2019, Japan's exports of it to South Korea fell 87.9 percent. South Korea bought more from the United States and Taiwan and made more at home.

Read it in Chemicals, Gases and Photoresist

One of the handful of companies that run data centers at global scale, such as Amazon, Microsoft, Google, Meta and Oracle.

They pay for the AI buildout. Alphabet, Amazon, Meta, Microsoft and Oracle spent $448.2 billion of capital in 2025, the sum of Epoch AI's quarterly figures.

Read it in Data Centers and PowerAlso in Systems and Networking

i-line is the coarsest of the main lithography lights, 365 nanometers from a mercury lamp, named for one line in the lamp's spectrum. It prints the widest features on a chip and much of a package.

SMEE, the established Chinese scanner maker, is strongest in i-line, and even there it holds about 4 percent of the world market.

Read it in LithographyAlso in Chemicals, Gases and Photoresist

A chip company that both designs its products and manufactures them in its own factories. Intel, Samsung and Micron are examples.

An integrated maker that also makes chips for other companies competes with its own customers. Its own products take the best capacity, so fewer customers trust it with a flagship design.

Read it in Foundries and Fabs

Immersion lithography prints with a thin layer of ultrapure water between the scanner's lens and the wafer. The water lets the lens focus light at a wider angle than air allows, so the same light prints finer lines. It is the most advanced form of deep ultraviolet lithography, one step below extreme ultraviolet.

Dutch export licensing covers the most advanced immersion scanners. Reuters reported in July 2026, citing one unnamed source, that a Chinese state-owned firm had started producing its own immersion scanners.

Read it in LithographyAlso in Chemicals, Gases and Photoresist, Transistors and the Front End, Who Controls the Chain

A change in the end use or the end user of an item inside one foreign country, defined at 15 CFR 734.16. Nothing crosses a border. A server legally imported into a country for one customer is transferred when it is resold, or repurposed, for another.

Controls on in-country transfers catch hardware diverted after it has arrived. So a license granted for a named Chinese customer does not cover the hardware if it passes to someone else. Reexports and in-country transfers of advanced chips to Macau or Country Group D:5 keep a presumption of denial, meaning a license will normally be refused (91 FR 1684). That holds even where an export from the United States would be reviewed case by case (91 FR 1684).

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Indium phosphide is a crystal grown from the metal indium and phosphorus. It gives off light when current passes through it, which silicon cannot do efficiently. The lasers inside the fastest optical modules are made of it.

China produced about 70 percent of the world's indium in 2025. In February 2025 it put indium under new export restrictions and began requiring export permits for indium phosphide substrates. In March 2026 Nvidia agreed to invest $2 billion each in Coherent and Lumentum, alongside purchase commitments for their lasers.

Read it in Systems and Networking

Inference is running a finished AI model to answer requests, such as a prompt. Training, a run of weeks on a cluster of accelerators, builds the model first. To write each word of an answer, the chip reads the whole model from memory, does a little arithmetic and waits for the next read. Training reuses each number it fetches, so it fetches little and computes a lot.

In inference, memory size and speed usually set how many people one chip can serve.

Read it in Memory and HBMAlso in Chip Design, EDA and IP, Who Controls the Chain

InfiniBand is a networking standard long used in supercomputers, with low delay and no dropped packets. AI clusters relied on it to link thousands of servers before Ethernet caught up, and Nvidia still sells both.

The choice between InfiniBand and Ethernet decides who sells the switch chips. Broadcom has doubled the bandwidth of its Ethernet switch chips with each generation since 2019.

Read it in Systems and Networking

A layer of wiring with no transistors, used as a miniature circuit board underneath several chips so they can be connected at a density no ordinary board could reach. It is either one piece of silicon or layers of fine copper wiring, often with small silicon bridges.

HBM connects over 1,024 or 2,048 wires, too many for a resin board, so memory and logic sit together on an interposer. Its area caps how much fits in one package. In April 2026 TSMC was producing CoWoS at 5.5 times the reticle, the largest area a lithography machine prints in one exposure.

Read it in Advanced PackagingAlso in Memory and HBM, Substrates and PCBs

A way of changing how silicon conducts by firing atoms into it. An ion implanter shoots charged atoms of boron, phosphorus or arsenic into the wafer, where they lodge just under the surface. The patches they land in then conduct the way the design needs.

Every modern chip process relies on it. Implanters are export-controlled. In February 2026 Applied Materials agreed to pay a penalty of about $252 million over implanters shipped to a Chinese customer on the Entity List.

Read it in Transistors and the Front End

In chip design, IP, short for intellectual property, means a ready-made block of circuitry, such as a processor core or a memory interface, that a design house licenses. Arm sells processor IP, and other firms sell the blocks that talk to memory, PCIe or another chiplet.

Each licensed block must be proven on a new process before a chip can use it. The memory interface is a demanding one, because it has to hold its timing across thousands of solder bumps into a stacked memory die.

Read it in Chip Design, EDA and IP

A letter from BIS to one named company imposing a license requirement on a specific export, without any rule being published. BIS's power to send one is written into the regulations themselves, for example 15 CFR 744.23(b), which lets BIS inform a person individually, with no amendment to the EAR.

It imposes a control at once, with no published rule. BIS imposed the April 2025 license requirement for Nvidia's H20 this way, and the public learned of it from Nvidia's own filing.

Read it in Who Controls the ChainAlso in Chip Design, EDA and IP

JEDEC is the industry body that writes the standards for memory chips, so that a memory stack from any maker fits any processor built to the same specification. Its HBM4 standard, published in April 2025, sets the width and speed of the interface.

Makers now ship HBM4 faster than the standard's 8 Gb/s per pin. Samsung's runs at 11.7, SK hynix's above 10 and Micron's above 11. Each customer runs its own qualification tests, so meeting the standard does not by itself win an order.

Read it in Memory and HBMAlso in Advanced Packaging

A kilowatt is a thousand watts. A megawatt is a thousand kilowatts, and a gigawatt a thousand megawatts, about the output of one large power station. A GB300 NVL72 rack draws up to 142 kilowatts. The largest data center campuses are planned in gigawatts.

AI deals are now counted in gigawatts too, as when OpenAI and Broadcom announced 10 gigawatts of accelerators. Power equipment now arrives more slowly than the chips.

Read it in Data Centers and Power

A bare chip tested thoroughly enough, before assembly, to be trusted inside something expensive. In an ordinary product a faulty chip wastes one chip. Inside a package that joins a dozen expensive pieces, one bad die throws away all of them.

As packages grow toward about ten large compute dies and 20 memory stacks, a bad die found only after assembly scraps more parts. So chipmakers move testing and burn-in, running chips hot to force early failures, back onto the wafer.

Read it in Test and AssemblyAlso in Metrology and Inspection

KrF is krypton fluoride, the gas in an older lithography laser that shines at 248 nanometers. KrF scanners print the coarser layers of a chip, where lines are far apart.

KrF tools print coarser layers such as implant layers. ASML sold 78 of them in 2025, and Canon also makes them.

Read it in LithographyAlso in Chemicals, Gases and Photoresist

A laminate is a stiff sheet made by pressing glass cloth and resin together, usually with copper foil bonded to its faces. It is the material a circuit board or a substrate core is cut from. A low-loss laminate absorbs little of the signal passing through the wires on it.

How much signal the laminate absorbs has become a main design limit on the boards that link GPUs.

Read it in Substrates and PCBs

A large power transformer is a machine that changes grid electricity from one voltage to another, for example from transmission voltage down to a level a data center can use. Switchgear is the heavy switching and protection equipment around it. Together they make up the substation at the gate of the campus.

In 2024 lead times of 36 months were commonly quoted, against under a year before the pandemic. Of the units put into US service in 2019, 82 percent were imported.

Read it in Data Centers and Power

Lead time is the wait between placing an order and receiving it. A wafer clears a leading-edge fab in months, while in 2024 a large power transformer commonly took three years.

Chip supply and power equipment are both constrained. Micron said in its report for the quarter to May 2026 that AI-driven memory and storage growth was outpacing industry supply. Waits for large power equipment run to years.

Read it in Data Centers and Power

The leading edge is the newest generation of chipmaking process in volume production. In 2026 that means the 3 nm and 2 nm nodes, made only by TSMC, Samsung and Intel. A leading-edge chip is one built on it.

Gate-all-around transistors are the design used at 2 nm, and only TSMC, Intel and Samsung make them in volume. In 2024 the United States put a worldwide license requirement on the technology for building them.

Read it in Transistors and the Front EndAlso in Chip Design, EDA and IP, Silicon and Wafers, Photomasks and Pellicles, Foundries and Fabs, Memory and HBM, Test and Assembly, Data Centers and Power, The Economics of AI Chips, Who Controls the Chain

A written carve-out in export rules that lets a shipment go without an individual license, if it meets stated conditions. The ones that matter for AI chips and chipmaking tools are NAC and ACA (15 CFR 740.8), HBM (740.25), AIA and LPP (740.27 and 740.29), IEC (740.24) and RPL (740.10). AIA and LPP let the top band of accelerators ship to allies, and elsewhere in small volumes. IEC covers countries that adopt matching controls, and RPL covers servicing and spare parts.

Exceptions let the US government adjust its controls without rewriting them and ease the rules for allies. License Exception IEC, added in September 2024, covers exports to and by countries that have put equivalent controls in place (89 FR 72926).

Read it in Who Controls the ChainAlso in Memory and HBM

An export rule that lets AI chips other than top-band data center chips ship to most of the world with no license and no advance notice. It covers the same chips as its companion exception NAC, and every destination except Macau, Country Group D:5 and firms headquartered in either. The top-band data center chips in ECCN 3A090.a are excluded. BIS split it from NAC at 15 CFR 740.8 in April 2024. The AI Diffusion rule widened it in January 2025 to the whole world outside Macau and D:5.

It lets these chips reach most of the world with no license or advance notice. NAC keeps a notice requirement for Macau and D:5. Before April 2024 NAC did both jobs, so an older table that shows one exception describes what is now two.

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License Exception ACM, for Advanced Compute Manufacturing, lets controlled AI chips and related items go without a license to private-sector firms that develop, make or store them. The items must be bound for customers outside Macau and Country Group D:5. It was created alongside License Exceptions AIA and LPP.

It keeps the AI Diffusion rule's worldwide license requirement from catching chips that are only passing through factories and warehouses on their way to an eligible customer.

Read it in Who Controls the Chain

License Exception AIA, for Artificial Intelligence Authorization, lets the top band of AI chips ship without a license to nineteen destinations. They are listed in supplement no. 5 to part 740, and the United States is among them. The AI Diffusion rule created it in January 2025 as the exception inside a worldwide license requirement.

BIS said in May 2025 that it would not enforce the AI Diffusion rule. But the rule was never repealed, so AIA still stands in the regulations. BIS says it enforces the worldwide requirement only for Country Groups D:1, D:4 and D:5 and for firms headquartered in D:5 or Macau.

Read it in Who Controls the Chain

An export rule that lets high bandwidth memory go to a packaging site with no license, to be packaged beside a chip. It applies if the memory's bandwidth density is below 3.3 GB/s per square millimeter, measured over the area of the package or stack. The exporter must be headquartered in the United States or Country Group A:5. If the memory is bound for Macau or Country Group D:5, the chip's designer must buy it. The stacks must go straight to the packaging site. It does not cover packaging at a facility in Macau or D:5 that also makes advanced-node chips. It sits at 15 CFR 740.25.

It lets Chinese packaging houses stay in the supply chain of American and allied chip designers. But a sale of the same stacks to a Chinese buyer still needs a license. HBM needs a license only for Macau and Country Group D:5, and the exception was written into the December 2024 rule that first controlled HBM (89 FR 96790).

Read it in Who Controls the ChainAlso in Memory and HBM

An export rule that lets a buyer almost anywhere receive a capped amount of top-band AI chips each year without a license. The cap is 26,900,000 TPP, the export rules' measure of computing power, per ultimate consignee per calendar year. Macau, Country Group D:5 and firms headquartered in either are excluded, and it does not cover transfers within a country. The AI Diffusion rule created it in January 2025, at 15 CFR 740.29.

It lets buyers outside the nineteen destinations in supplement no. 5 to part 740 take top AI chips in small amounts with no license application. BIS said in May 2025 that it would not enforce the AI Diffusion rule, but it withdrew none of the text. So LPP still stands in the regulations beside the rule's other exceptions, AIA and ACM, and the nineteen-destination list.

Read it in Who Controls the Chain

An export rule that lets AI chips other than top-band data center chips ship to Macau and Country Group D:5, and to firms headquartered there, with no license. The exporter must notify BIS at least 25 calendar days ahead, and the shipment can go if BIS does not say a license is needed. The top-band data center chips in ECCN 3A090.a and the memory in 3A090.c are excluded. It sits at 15 CFR 740.8.

It lets these chips reach the restricted destinations without a license application. Since April 2024 section 740.8 has held two exceptions, NAC for the restricted destinations and ACA for everywhere else.

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Taking heat out of a processor by pumping liquid through a cold plate on the chip package, instead of blowing air across a finned heatsink. A building loop then carries the heat outdoors.

Nvidia's GB300 NVL72 rack is liquid cooled, and its Rubin platform is entirely liquid cooled. Nvidia says every cloud provider and data center operator building for Rubin is moving to liquid cooling.

Read it in Data Centers and Power

Printing a circuit pattern onto a wafer by shining light through a patterned plate and projecting a shrunken image of it onto a light-sensitive coating. It works like photography at the scale of nanometers, repeated once for every layer of the chip.

Only one company, ASML, makes the machines for its finest layers, and those layers set how densely transistors and wires pack.

Read it in LithographyAlso in Silicon and Wafers, Chemicals, Gases and Photoresist, Photomasks and Pellicles, Deposition and Etch, Transistors and the Front End, Advanced Packaging, Substrates and PCBs, Test and Assembly, Who Controls the Chain

A logic chip is one that computes, such as a processor, a graphics processor or an AI accelerator. Memory chips, such as DRAM and NAND flash, store data instead.

US export rules set separate lines for logic and memory. The October 2022 rule covered equipment for fabs in China making logic chips at 16/14 nm or below. It also covered fabs making DRAM at 18 nm half-pitch or below, or NAND with 128 or more layers. ASML's 2025 system sales were €16,054.1 million to logic chipmakers and €8,420.2 million to memory makers.

Read it in Foundries and FabsAlso in Silicon and Wafers, Deposition and Etch, Metrology and Inspection, Transistors and the Front End, Advanced Packaging, Substrates and PCBs, Test and Assembly, The Economics of AI Chips, Who Controls the Chain

A lot is the batch of wafers a fab moves through its machines together, usually 25 in one sealed carrier. Recipes, inspections and yield are tracked lot by lot.

A fab decides how many wafers in each lot it can afford to inspect. That choice sets how much it spends on process control, the measuring that keeps each step on target.

Read it in Metrology and InspectionAlso in Chemicals, Gases and Photoresist, Memory and HBM

Macau is a Chinese city with its own customs territory, like Hong Kong, so goods can enter it under separate rules. US export controls name China and Macau together to close that route, and treat a firm headquartered in either the same way.

Under the US rules on advanced AI chips, a chip that needs a license for China needs one for Macau too.

Read it in Who Controls the ChainAlso in Metrology and Inspection, Memory and HBM

A mask blank is a photomask before any pattern is on it. It is a six-inch square of very flat glass carrying the film that the pattern will be cut into. For extreme ultraviolet that film sits on a mirror of about forty pairs of ultrathin layers, and a particle buried in the mirror cannot be repaired.

The Japanese glassmaker AGC says only three firms supply EUV blanks, and AGC and Hoya, both Japanese, are two of them. AGC spent more than a decade meeting the blank's requirements before it began mass production in 2017.

Read it in Photomasks and PelliclesAlso in Silicon and Wafers

A mask shop is the factory that turns a finished chip design into its set of photomasks. It writes each plate with an electron beam, inspects it and repairs it.

No chip can be printed until its masks are made. Chipmakers such as TSMC and SMIC run shops of their own, and independents such as Photronics sell to them and to others.

Read it in Photomasks and PelliclesAlso in Chip Design, EDA and IP, Lithography

A mask writer is the machine that uses electrons to draw a chip's pattern into the resist on a photomask blank. A single-beam writer flashes one shape at a time, while NuFlare's multi-beam writer for the most advanced masks controls 260,000 beams at once.

No new chip can be printed until its masks are written. In 2023 Intel said advanced EUV requires multi-beam mask writers and called Austria's IMS Nanofabrication the established leader in them. Counting all electron-beam mask writers, CSET put IMS at 46.6 percent of 2025 sales and Japan's NuFlare at 39.2 percent.

Read it in Photomasks and PelliclesAlso in Chip Design, EDA and IP

A mature node is an older chipmaking process, 28 nm and above, that has run for years and competes on price. Most of the world's wafers come off these lines, making power chips, analog parts and microcontrollers.

China held 33 percent of the world's logic capacity at 28 nm and above in 2022. In the five years before May 2024, Chinese companies invested $63 billion in 73 fabs, mostly for chips above 28 nm, SIA and BCG reported.

Read it in Foundries and FabsAlso in Chip Design, EDA and IP, Silicon and Wafers, Who Controls the Chain

Memory bandwidth density is how much data a memory stack can move each second divided by the area of its package or stack, in gigabytes per second per square millimeter. The December 2024 rule controls any stack above 2, and BIS said every HBM stack then in production exceeded that.

One threshold catches every HBM stack in production, including stacks made outside the United States, so the control reaches all three makers, SK hynix, Samsung and Micron. A license exception still lets stacks below 3.3 go straight to a chip designer's packaging site. HBM already packaged with a processor falls under the chip rules instead.

Read it in Memory and HBM

The widening gap between how fast a processor can calculate and how fast memory can feed it numbers to work on. The cost of arithmetic has fallen faster than the cost of moving numbers.

An AI chip reads its whole model from memory for each word it writes, so memory size and speed usually set how many people one chip can serve. Memory is also about half the cost of building an Nvidia B200, on Epoch AI's estimate.

Read it in Memory and HBM

A metal-oxide resist is a photoresist built on clusters with a tin-oxide core. It absorbs more extreme ultraviolet light than a chemically amplified resist. That helps because an EUV dose arrives as relatively few photons.

Resist makers aim it at High-NA tools and the tightest pitches. The Japanese resist maker JSR agreed in 2021 to buy Inpria, an Oregon maker of these resists. In 2024 a company owned by a Japanese state-backed fund took 84.36 percent of JSR.

Read it in Chemicals, Gases and Photoresist

METI is Japan's Ministry of Economy, Trade and Industry, the ministry that writes Japan's export controls and funds its chip industry. It put advanced chipmaking equipment under export license from July 2023. It also supports the chipmaker Rapidus and new capacity for mask blanks, the glass plates that photomasks are made from.

Japan's controls apply to every destination and name no country, and METI decides them.

Read it in Who Controls the ChainAlso in Silicon and Wafers, Chemicals, Gases and Photoresist, Photomasks and Pellicles

Measuring what a factory actually built: how wide a printed line came out, how thick a film is, whether this layer sits exactly on top of the last one. Inspection is the related job of finding flaws.

A fab that cannot buy sensitive inspection tools finds fewer of the defects that lower its yield, so its yield rises more slowly. KLA held 56.8 percent of the market for these tools in 2025, by CSET's count.

Read it in Metrology and InspectionAlso in Who Controls the Chain

A microbump is a dot of solder that joins a die to the interposer or substrate beneath it. In Intel's 2.5D packages microbumps sit 36 microns apart, less than half a hair's width. Each one is an electrical connection that has to survive as the package heats and cools.

Their spacing limits how many connections fit between stacked or neighboring chips. Hybrid bonding, which joins copper straight to copper, would pack connections far closer, but it is not yet ready for HBM.

Read it in Advanced PackagingAlso in Chip Design, EDA and IP, Metrology and Inspection

mm2 means square millimeters, the unit chip areas are given in. A lithography scanner prints at most 858 mm2 in one shot, and each compute die in an Nvidia B200 is about 800 mm2. TSMC plans to start making CoWoS packages with interposers 14 times the size of one scanner shot in 2028.

Yield, the share of dies that work, falls as die area grows, so the cost of each working chip rises faster than its area.

Read it in The Economics of AI ChipsAlso in Chip Design, EDA and IP, Transistors and the Front End, Memory and HBM, Advanced Packaging

Model weights are the billions of numbers that make up a trained AI model. They are the file that runs on the chips, so copying the weights copies the model.

A chip reads the model's weights from memory for each word it writes, so bigger models need more HBM. The AI Diffusion rule also made frontier model weights a controlled item, ECCN 4E091.

Read it in Who Controls the Chain

MOFCOM is China's Ministry of Commerce, the ministry that writes and administers China's own export controls. Its notices put gallium, germanium and seven rare earths under license. In December 2024 it banned exports of gallium, germanium, antimony and superhard materials to the United States.

China's retaliation targets inputs such as these minerals, and MOFCOM signs each notice.

Read it in Who Controls the ChainAlso in Systems and Networking

Building one chip layer in several patterning steps, because a single exposure cannot print lines that close together. It comes in two kinds. Litho-etch multipatterning splits the layer's pattern across two or three masks, then prints and etches each part separately. Self-aligned double or quadruple patterning prints one coarser pattern, then deposits and etches thin spacer films along its edges to halve or quarter the line spacing. Cut masks then remove the parts of lines the circuit does not need.

SMIC makes its 7 nm-class chips without extreme ultraviolet machines by multipatterning on deep ultraviolet tools. TSMC's first 7 nm process and Intel 7 were also made without extreme ultraviolet light. Every extra mask or spacer step adds cost and machine time, and each extra litho-etch exposure adds a chance that parts of the layer misalign.

Read it in LithographyAlso in Foundries and Fabs, Who Controls the Chain

NAND is the memory that keeps data when the power is off. It is the storage inside a phone, a laptop drive or a data center disk. 3D NAND stacks its cells in many layers, made by etching holes far deeper than they are wide. It is slow next to DRAM and is not used inside an AI accelerator.

Under the October 2022 US rules, items subject to US export rules bound for a fab in China that makes NAND with 128 or more layers need a license. The proposed MATCH Act would name YMTC, a Chinese NAND maker, in the law itself.

Read it in Memory and HBMAlso in Deposition and Etch, Metrology and Inspection, Who Controls the Chain

A nanometer is a billionth of a meter. A micron, or micrometer, is a thousand nanometers, an angstrom is a tenth of a nanometer, and a picometer is a thousandth. Lithography light is measured in nanometers, package bumps in microns, and mirror flatness in picometers.

Node names such as 2 nm no longer describe any feature that size, but the physical limits of printing and stacking are still measured in these units.

Read it in LithographyAlso in Chip Design, EDA and IP

Neon, mixed with krypton or argon and fluorine, is the gas inside the lasers that give deep ultraviolet scanners their light. A fab uses it by the cylinder, and those scanners cannot print without it.

Ukraine supplied about 70 percent of the world's neon before Russia invaded in 2022. Many chipmakers had added to their gas stockpiles after Russia annexed Crimea in 2014, and several reported adequate supplies from China.

Read it in Chemicals, Gases and Photoresist

Nitrogen trifluoride is a gas that cleans process chambers between wafers. Split apart in a plasma, it releases fluorine that scours the deposits off the inside of the chamber.

A shortage of any one chemical can stop a fab. SK Specialty of South Korea has made nitrogen trifluoride since 2001, when it became the first company to produce the gas there.

Read it in Chemicals, Gases and Photoresist

Nm-class, as in 7 nm-class, means a process roughly as dense as the foundries' 7 nm generation. The label is used when a maker's own name for the node is different.

China's SMIC builds its 7 nm-class processes without extreme ultraviolet machines, and its most advanced, N+3, reaches the density of TSMC's 6 nm-class process.

Read it in Transistors and the Front EndAlso in Foundries and Fabs, Who Controls the Chain

The name a foundry gives one generation of its manufacturing process. The number in the name no longer measures anything on the chip. SMIC's N+3, a 7 nm-class process, spaces its narrowest wires closer together than Intel's Panther Lake chips on 18A do.

Comparing two foundries by node name says little. Each foundry also picks its own baseline for the density gains it claims.

Read it in Transistors and the Front EndAlso in Photomasks and Pellicles, Foundries and Fabs, Who Controls the Chain

Nvidia's rack-sized product, with 72 accelerators in 18 compute trays joined through nine switch trays so that software can treat the whole rack as one computer. The GB300 version draws up to 142 kilowatts.

AI capacity is built and costed by the rack. In July 2026 SemiAnalysis put the cost of owning a Vera Rubin NVL72 at $3.57 per GPU-hour, against $1.84 for a GB200 and $2.36 for a GB300.

Read it in Systems and NetworkingAlso in Memory and HBM, Data Centers and Power, The Economics of AI Chips

Nvidia's own high-speed connection between its accelerators, which lets dozens of them act as one. NVLink 6 carries 3,600 gigabytes per second per GPU, according to Nvidia's January 2026 Rubin launch.

Nvidia controls it, while more than 50 makers of systems and components build around its racks. Since May 2025 its NVLink Fusion program has let other firms' custom chips connect to Nvidia GPUs over NVLink, and Fujitsu and Qualcomm plan CPUs that do so. UALink is a published open rival.

Read it in Systems and Networking

An ODM, for original design manufacturer, is a firm such as Foxconn, Quanta or Wistron that designs and builds servers and racks to a customer's specification. The customer's name goes on the box. A contract manufacturer does the assembly only.

More than 50 makers of systems and components were gearing up for Nvidia's Vera Rubin NVL72 rack in October 2025, Nvidia said. In its filing for the quarter to July 2026, Nvidia said the complexity of producing its data center systems had caused production delays.

Read it in Systems and Networking

An oligopoly is a market with only a few sellers, so each one's decisions move the price. A duopoly has two. DRAM, industrial gases, substrates and chip testers are all oligopolies.

The fewer the sellers, the more one accident or one license decision moves the market. With a single seller, losing that seller stops the buyer's production line.

Read it in Memory and HBM

Operating margin is the share of revenue left after paying both the cost of making the product and the cost of running the company, research and sales included. It is lower than gross margin, which counts only the cost of making.

SK hynix's earnings release gives no gross margin, only an operating margin, which was 76 percent in the June 2026 quarter.

Read it in The Economics of AI ChipsAlso in Silicon and Wafers, Lithography, Foundries and Fabs

A small device that turns electrical signals into laser light for sending down a glass fiber, and turns them back at the far end. Every network link longer than a few meters in a large AI cluster needs one at each end.

A cluster needs several for each accelerator. One design for 100,000 H100s uses 98,304 just to link its GPUs to the first tier of switches. Chinese firms assemble the modules in volume, but the lasers inside them were scarce in 2026.

Read it in Systems and NetworkingAlso in The Economics of AI Chips

A contract firm that takes finished wafers, cuts them into chips, seals the chips into packages and tests them. It is the back end of chipmaking, done for hire.

Every chip passes through assembly and test. Yet in the June 2026 quarter Amkor earned a gross margin of 16.8 percent, and ASE's packaging and test segment 27.3 percent. In a TrendForce ranking cited by CSET, four of the ten largest of these firms by 2024 revenue are headquartered in China.

Read it in Test and AssemblyAlso in Advanced Packaging

How precisely one printed layer of a chip lands on top of the layer beneath it. Before each exposure the scanner finds marks printed in earlier layers and lines the new layer up on them to within a few nanometers, across a disc 300 millimeters wide.

Misalignment can ruin whole regions of a wafer, so overlay is one of the specifications that separates an advanced printing machine from an ordinary one. Each extra pass on a layer is another chance to misalign.

Read it in Metrology and InspectionAlso in Lithography

Panel-level packaging builds packages on a large rectangular sheet instead of a round wafer, so far less area is wasted at the edges and many more packages fit on one carrier. It gets around the size limits of a 300 mm wafer.

Powertech, a Taiwanese assembly and test firm, aims to run the first panel-level packaging line for AI chips in 2027.

Read it in Advanced PackagingAlso in Test and Assembly

PCIe is the standard connector and link that joins a processor to the cards inside a computer, an accelerator included. In an AI server it carries data between the host processor and the GPUs, while faster private links join the GPUs to each other.

The PCIe block is licensed IP that has to be proven on each new node before a chip can use it.

Read it in Chip Design, EDA and IP

A process design kit, or PDK, is the set of files a foundry gives designers to describe exactly what its factory can print on one process, or node. It gives the sizes, spacings and electrical behavior of every feature. Design software is checked against it before a chip is accepted.

Foundries develop each kit with the design-software vendors about two years before production starts and specify which tools customers must use for tape-out.

Read it in Chip Design, EDA and IP

A thin transparent membrane on a frame above a photomask, the patterned plate a chip layer is printed from. Dust settles on it, far enough out of focus that it does not print, so the pattern stays clean. It works like a lens cap a photographer can shoot through.

Pellicles already work in high-volume EUV manufacturing. But no material is completely transparent to EUV light, and the light crosses the membrane twice, so every pellicle costs some output. Carbon nanotube membranes, which passed up to 97 percent of the light in one crossing in imec's 2020 tests, are the next step.

Read it in Photomasks and Pellicles

An export control test of how densely a chip packs its computing power. It divides the chip's TPP, the export rules' measure of computing power, by its applicable die area in square millimeters. That area counts all logic dies made on a process with non-planar transistors, such as FinFETs. The test applies only to a chip that reaches 1,600 TPP. It replaced the 2022 test, which was based on interconnect bandwidth, the speed at which a chip exchanges data with its neighbors.

It closed a gap that Nvidia's China-specific chips, such as the A800 and H800, had used. Nvidia had designed those chips to stay under the 2022 interconnect-speed threshold. The top band, ECCN 3A090.a, now starts at 4,800 TPP, or at 1,600 TPP with a performance density of 5.92 (88 FR 73458).

Read it in Who Controls the Chain

The master template for one layer of a chip: a quartz plate, or for the shortest wavelengths a mirror, that carries the pattern projected onto the wafer. A chip needs dozens of them, at least one per layer. In July 2022 SemiAnalysis put a full set above $1 million at 28 nm and above $10 million at 7 nm. In May 2026 it put a leading-edge set at $40 million.

The cost of a mask set limits which chips are worth making on a leading-edge process at all. Only three firms supply the blank plates for EUV masks, and two of them are Japanese.

Read it in Photomasks and PelliclesAlso in Chip Design, EDA and IP, Silicon and Wafers, Lithography

The light-sensitive coating that records a chip's pattern during lithography. A machine spins a thin film of it across the wafer. Light shone through a stencil changes the film where it lands, and a wash removes those parts. What remains shows the next machine where to etch.

Every printed layer of a chip uses it. Each resist is tuned to the layers it prints, and even one that passes the first time takes seven to 17 months to approve in a fab. Japanese companies held 78 percent of world sales in 2023. In 2024 an investment vehicle of a Japanese state-backed fund bought 84.36 percent of the resist maker JSR.

Read it in Chemicals, Gases and PhotoresistAlso in Silicon and Wafers, Lithography, Deposition and Etch

Pitch is the distance from one line on a chip to the next, center to center, so it counts the line and the gap together. Half-pitch is half that. A 16 nm pitch means lines 16 nanometers apart. The 2022 US rules set a DRAM threshold at 18 nm half-pitch.

Unlike a node name, pitch measures something physical on the chip. But SemiAnalysis calls a single pitch an incomplete metric for comparing processes.

Read it in Transistors and the Front EndAlso in Metrology and Inspection

A plasma is a gas energized until some of its atoms or molecules break into charged particles. Most etch steps and many deposition steps happen in a plasma that an electric field makes inside a vacuum chamber, though batch furnaces mostly work without one. In the chamber, neutral fragments called radicals do most of the chemistry, and charged ions give etch its direction. In an extreme ultraviolet machine, a laser vaporizes droplets of molten tin into a plasma that gives off the 13.5-nanometer light.

Export controls describe each tool by the process it is designed to run. An extreme ultraviolet source has to make its tin plasma 50,000 times a second to give enough light for production.

Read it in Deposition and EtchAlso in Chemicals, Gases and Photoresist, Lithography

Polysilicon is purified silicon that has not yet been grown into one crystal. It comes as gray rods made of many small crystals. It is the raw material that is melted down to pull the single crystal a wafer is cut from. The same material, at lower purity, goes into solar panels.

China made about 93 percent of the world's polysilicon in 2023. But the German wafer maker Siltronic names five major suppliers of the electronic-grade kind for 2025, and none of them is Chinese.

Read it in Silicon and Wafers

A power shelf is a slide-in unit in a rack that converts the incoming supply to the voltage the boards use and feeds it to the busbar. A GB300 NVL72 rack draws its 142 kilowatts through eight of them at 33 kilowatts each.

Many firms supply the shelves and the boards behind them. The large transformers upstream commonly took three years to arrive in 2024.

Read it in Data Centers and Power

A presumption of approval means a license is still required but will normally be granted. It is the opposite of a presumption of denial, and one rule can contain both. HBM license applications for Macau and Country Group D:5 are presumed approved when neither the buyer nor its ultimate parent is headquartered in either place, and presumed denied otherwise (15 CFR 742.6(b)(10)(ii)).

The split lets HBM reach plants in China owned by firms headquartered elsewhere while holding it back from Chinese-owned buyers.

Read it in Memory and HBM

A license review policy in which the reviewing agencies start from the position that an application should be refused. An application can still be filed and will be considered, but the exporter has to overcome that starting position. It is the general policy for advanced computing chips going to China and Macau under 15 CFR 742.6(b)(10), and for most Entity List entries. Since January 2026 export applications for some less powerful chips, such as the H200, are reviewed case by case instead.

The difference between a presumption of denial and a prohibition decides whether a company files at all. Under a presumption of denial an application can still be made, but under a prohibition it cannot.

Read it in Who Controls the ChainAlso in Memory and HBM

A printed circuit board is the flat green or black card that electronic parts are soldered onto, with its wiring etched from copper sheets and stacked in layers. Boards for AI servers can run past 30 layers.

It carries the power and the links between GPUs. How much signal its laminate absorbs is now a main design limit.

Read it in Substrates and PCBsAlso in Memory and HBM, Advanced Packaging, Test and Assembly, Systems and Networking, The Economics of AI Chips

A circuit board carrying thousands of fine needles that press onto the contact pads of a chip while it is still part of the wafer. A tester drives signals into the chip through the needles. Every card is custom-built for one chip design.

Because each card is custom-built and slow to qualify, probe card supply and lead time can limit how fast a new accelerator or memory stack reaches full production.

Read it in Test and Assembly

Physical vapor deposition, or PVD, coats a wafer with metal in a vacuum. It knocks atoms off a solid slab of metal, the sputtering target, and they fly across and land on the wafer as a thin film. It lays down the metal barriers and seed layers under a chip's copper wiring.

Every copper wire needs that barrier, because copper seeps into the insulator around it. JX Advanced Metals puts its own share of the world market for semiconductor sputtering targets at about 65 percent as of fiscal 2026.

Read it in Deposition and EtchAlso in Chemicals, Gases and Photoresist

Qualification is the testing a fab or a customer runs before it will accept a new material, tool or supplier. A resist, a slurry, a wafer source or a memory stack is approved for a set use, such as one layer in one fab's process, and switching means running the tests again.

Even a resist that passes the first time takes seven to 17 months to approve, the Semiconductor Industry Association wrote in 2023, so a second source is slow to add.

Read it in Chemicals, Gases and PhotoresistAlso in Test and Assembly

The standard steel frame that computing equipment is bolted into in a data center, roughly the size of a wardrobe. For AI, a whole rack is wired and sold as one machine, so the rack itself is the product.

A GB300 NVL72 rack draws up to 142 kilowatts. Nvidia's 800-volt power design is intended for racks of more than a megawatt from 2027. A megawatt rack needs a different busbar, the metal bar that carries power to its equipment. It also changes the weight the floor must bear, the coolant flow and the energy stored in the rack to keep its power draw steady.

Read it in Data Centers and PowerAlso in Memory and HBM, Substrates and PCBs, Systems and Networking, The Economics of AI Chips

A ramp is the months in which a new process or product climbs from a few wafers a week to full output while the share of working chips rises. Yield is lowest at the start of the ramp and improves as engineers find which steps lose dies.

Whether a new process makes a profit or needs a subsidy depends on its yield in the first year.

Read it in Foundries and FabsAlso in Memory and HBM, Systems and Networking

The rare earths are a group of metals, including samarium and yttrium, that go into the strong magnets in motors, disk drives and wind turbines, and into some lasers and glass.

Beijing put seven of them under export license in April 2025. In October 2025 it claimed jurisdiction over foreign goods containing Chinese rare earths worth 0.1 percent or more of their value. That rule is suspended until 10 November 2026.

Read it in Who Controls the ChainAlso in Silicon and Wafers

A redistribution layer is a thin sheet of fine copper wiring, laid down in resin, that spreads a die's tightly spaced connections out to a wider pattern the package can handle. CoWoS-R and CoWoS-L use it in place of a full silicon interposer.

TSMC pushed packages past 3.3 times the reticle size by swapping silicon for redistribution wiring.

Read it in Advanced Packaging

Shipping an item that falls under US export rules, the EAR, from one foreign country to another. The term is defined at 15 CFR 734.14. A memory stack subject to the EAR moving from Korea to China is a reexport, and it needs the same US license a shipment from Texas would.

The reexport rule lets US controls follow an item after it leaves the United States, so they reach trade between two foreign countries.

Read it in Who Controls the Chain

The patterned plate whose image a lithography machine projects onto the wafer, one chip layer at a time. In practice it means the same as photomask, but the word reticle stresses that the machine steps the same image again and again across the wafer.

One exposure from a reticle prints at most 26 by 33 millimeters of the wafer, and every large AI chip has to be designed around that limit.

Read it in Photomasks and PelliclesAlso in Chip Design, EDA and IP, Advanced Packaging, The Economics of AI Chips

The largest chip a lithography machine can print in a single exposure, about 858 square millimeters, or 26 by 33 millimeters. It is set by the machine's optics and is the same for every design. The newer High-NA EUV machines print half that area.

Many leading AI accelerators, Nvidia's Blackwell among them, need more circuitry than this, so they are split into several dies, separate pieces of silicon, and joined back together inside a package.

Read it in Advanced PackagingAlso in Chip Design, EDA and IP, The Economics of AI Chips

RISC-V is an open instruction set, the list of basic commands a processor understands, that anyone may use without a license. Companies build their own processor cores on it, and Nvidia now uses such cores for small control tasks inside every GPU.

It is the license-free alternative to Arm's processor designs.

Read it in Chip Design, EDA and IP

RTL, for register-transfer level, is the code in which a chip is first written. It is text, in a language such as SystemVerilog, that describes what every storage element holds on every tick of the clock. Software later turns it into transistors and wires.

It defines what the chip does. A large team checks it in simulation and emulation before tape-out, because a mistake found later needs new masks.

Read it in Chip Design, EDA and IP

The network that joins thousands of accelerator groups into one cluster, running at hundreds of gigabits per second over Ethernet or InfiniBand. Its Ethernet versions use the same standard as ordinary data center networks.

It lets thousands of accelerators train one model together. InfiniBand was the main scale-out network when AI clusters were small. But Ethernet capacity has since grown quickly, as Broadcom doubled the bandwidth of its switch chips every generation.

Read it in Systems and Networking

The network that joins a group of accelerators, from a few dozen in one rack to thousands, so a model too large for a single chip can be spread across them. It runs at terabytes per second. In Nvidia's GB300 NVL72 each GPU has nine times as much bandwidth on it as on the scale-out network.

The bandwidth of this network limits how efficiently a large model trains. Nvidia sells its own NVLink for it, and UALink is a published open standard that competes with NVLink.

Read it in Systems and Networking

A scanner is the lithography machine itself. It holds the photomask up to a light source and projects a shrunken image of one layer onto the wafer. Mask and wafer sweep past each other in a narrow slit of light. An older stepper exposes the whole mask image at once instead of scanning. A standard EUV scanner sells for around $200 million.

ASML makes every EUV scanner in the world, so a rule aimed at its scanners reaches all advanced chipmaking.

Read it in LithographyAlso in Chip Design, EDA and IP, Chemicals, Gases and Photoresist, Photomasks and Pellicles, Transistors and the Front End, Foundries and Fabs, Advanced Packaging, Substrates and PCBs, Test and Assembly, The Economics of AI Chips

A second source is a second supplier qualified for the same part or material, so that a fab can keep running if the first one stops shipping. A single-source part has none, and adding one means joint development and a fresh qualification.

When Japan put three chemicals under export licenses for South Korea in 2019, South Korea bought more from other countries. Output of all three chemicals rose at South Korean firms and at Japanese companies' affiliates in South Korea.

Read it in Chemicals, Gases and Photoresist

A SerDes, for serializer-deserializer, is the circuit at the edge of a chip that turns many slow parallel signals into one very fast stream over a single pair of wires. A SerDes at the other end turns the stream back into parallel signals. Every link out of an accelerator, to another chip, a switch or an optical module, runs through one.

SerDes speed sets how much data a chip can move. Many chip designers license the blocks as IP, and each design has to be proven in silicon on every new process.

Read it in Systems and Networking

Signoff is the final set of automated checks a chip design must pass before tape-out. Static timing analysis checks that every signal arrives in time at the clock speed promised. Physical verification checks that every shape in the layout can be printed.

A foundry accepts only layouts that pass physical verification against its rules. At advanced nodes, Synopsys holds more than 90 percent of timing signoff, and Siemens more than 85 percent of physical verification.

Read it in Chip Design, EDA and IPAlso in Foundries and Fabs

A silicon bridge is a small sliver of silicon carrying dense wiring. It is set into the package only where two dies need thousands of connections between them, so the rest of the package can use cheaper wiring. Intel calls its version EMIB, and TSMC's CoWoS-L uses the same idea.

Bridges let a package grow past a single interposer's size limit, and CoWoS-L uses them to package Nvidia's Blackwell and Rubin chips. The bridges in Blackwell needed very high placement accuracy, and packaging issues limited its supply.

Read it in Advanced PackagingAlso in Substrates and PCBs

The argument that Taiwan's lead in advanced chipmaking deters an attack on the island, because so many countries rely on its chips.

The idea is central to debate about Taiwan's security, and it is contested. It holds only while Taiwan's chipmaking is hard to replace, so Taiwan keeps its newest chip processes at home first while the United States pushes for more chipmaking on its own soil.

Read it in Who Controls the Chain

The stated design of US technology controls: tightly restrict a narrow set of items that genuinely matter to national security, and leave the rest of trade alone.

It gives critics and defenders a test for whether export controls remain targeted security policy or have become general industrial policy.

Read it in Who Controls the Chain

A system on a chip, or SoC, is a single chip that combines processor cores, a graphics processor and other circuit blocks that a device needs. The main processor in a smartphone is one.

Makers of chip testers split their market in two. SoC testers check processors and other non-memory chips, and memory testers check memory. Advantest put SoC testers at about $6.9 billion of a $9.0 billion tester market in 2025.

Read it in Test and Assembly

Specialty gases are the gases a fab uses in small amounts, each for one job. Silane, for example, carries silicon into the chamber to build a film, and nitrogen trifluoride cleans the chamber. They arrive in cylinders. Bulk gases, such as nitrogen and oxygen, come by pipeline or from plants built at the fab.

Specialty gases are shipped to the fab in cylinders, so a government or a war can cut them off. Ukraine supplied about 70 percent of the world's neon before Russia invaded in 2022.

Read it in Chemicals, Gases and Photoresist

SRAM is the fast memory built from transistors on the logic chip itself, used as a cache that holds the numbers a processor is about to need. It is far faster than the memory stacks beside the chip and holds far less.

The cell that holds one bit has barely shrunk since the 5 nm node, which limits how much cache a designer can afford to put on an accelerator.

Read it in Transistors and the Front EndAlso in Chip Design, EDA and IP, Advanced Packaging

The test for whether an item falls under US export rules at all. Under 15 CFR 734.3 it covers anything in the United States and anything of US origin wherever it is. It also covers foreign-made goods that contain more than a permitted share of controlled US content, and foreign-made goods caught by a foreign direct product rule. The test applies to the item, whatever the seller's nationality.

The rules follow the item, so a Dutch or Korean firm shipping between two foreign countries can still need a US license.

Read it in Who Controls the Chain

A four-band rating of how hard it would be for a well-funded state or firm, starting today, to build an alternative to the leading suppliers at one stage of the supply chain. It is judged against four written tests. Easy: a second supplier is qualified, meaning approved by customers, and shipping today at the leading node, the most advanced process. Moderate: a second supplier exists but is not yet qualified at the leading node, and closing the gap takes about two to five years. Hard: no second supplier exists at the leading node, the path to one is known, and closing the gap takes five to ten years. Very hard: no second supplier exists, and the path depends on physics, decades of unwritten know-how or protected intellectual property. No one has yet repeated what the leaders did, and closing the gap takes ten years or more. The years are always counted for that same well-funded state or firm, and the count stops at qualification, which comes well after a prototype.

It says how long a rival or a government would need to replace a stage. The debate over export controls turns on that question.

The small, dense circuit board at the base of a chip package. The chips sit on it, and it spreads their microscopic connections out to the millimeter-scale solder balls a motherboard can accept. It is built up layer by layer from epoxy film, laser-drilled holes and plated copper.

A handful of firms, most of them in Asia, build these substrates for others. As packages grow, a substrate warps more and needs more layers, so fewer come out working.

Read it in Substrates and PCBsAlso in Advanced Packaging, Test and Assembly, The Economics of AI Chips

The moment a chip design is declared finished and the pattern files are sent to the factory to be written into masks. The name survives from when the data physically left on a reel of magnetic tape.

Each revision after tape-out, called a respin, needs at least some new masks. In May 2026 SemiAnalysis put a single respin at leading-edge nodes at $50 million to $100 million, so designers check everything they can before tape-out.

Read it in Chip Design, EDA and IP

TC-NCF and MR-MUF are two ways of joining the thinned memory chips in an HBM stack. In TC-NCF, thermocompression with non-conductive film, each chip is pressed onto the one below under heat, with a thin insulating film between them. Samsung uses it for its twelve-high HBM3E. In MR-MUF, used by SK hynix, the chips are stacked first, and a liquid protective material is injected between them and hardened.

Thinner chips and taller stacks warp more easily, and both methods aim to control that. SK hynix says its Advanced MR-MUF also dissipates heat well.

Read it in Memory and HBM

Thermocompression bonding presses one die onto another, or onto a substrate, under heat and force until the tiny solder bumps between them melt and join. It is how memory dies are stacked to make high bandwidth memory (HBM) and a growing way to place chiplets on a package.

ASMPT says it remained the leader in these bonders in 2025, when its revenue from them rose about 146 percent. It aims for 35 to 40 percent of a market it puts at $1.6 billion in 2028.

Read it in Advanced PackagingAlso in Test and Assembly

Throughput is how many wafers a machine can process in an hour. ASML's NXE:3800E EUV scanner reaches 220.

Throughput sets the cost of each layer and how many lots, or batches of wafers, a fab can afford to inspect. Brighter EUV light sources and multi-beam inspection tools both aim to raise it.

Read it in LithographyAlso in Metrology and Inspection

Total processing performance, the measure US export rules use for a chip's computing power. It starts from the number of multiply-accumulate operations, a multiply followed by an add, that the chip does each second. That number is doubled, multiplied by the number of bits in each operation, and added up across every processing unit on the chip. The definition is in ECCN 3A090, in supplement no. 1 to 15 CFR part 774.

The export rules for chip sales to China draw their lines in TPP. The top band, 3A090.a, starts at 4,800 TPP, or at 1,600 TPP with a performance density of 5.92. Since 15 January 2026, export applications for chips below 21,000 TPP and 6,500 GB/s of total DRAM bandwidth, such as the H200, are reviewed case by case for end users in China and Macau (91 FR 1684).

Read it in Who Controls the Chain

Google's own AI chip, designed in-house for its data centers and cloud service. Its eighth generation, announced in April 2026, is split into two chips, the TPU 8t for training and the TPU 8i for inference.

It shows that a large buyer can design its own alternative to chips sold on the open market. Ironwood, the seventh generation, carries 192 GB of memory per chip, six times its predecessor's. Google says the TPU 8t and TPU 8i deliver up to twice Ironwood's performance per watt.

Read it in Chip Design, EDA and IPAlso in Advanced Packaging, Systems and Networking, Data Centers and Power

The switch every chip is built from. Current runs through a channel between two terminals. A voltage on a third terminal, the gate, opens or closes that path, much as a tap opens or closes a pipe. One Nvidia Blackwell part contains 208 billion of them.

The whole chip supply chain exists to make transistors smaller, faster and less leaky. Only three companies, TSMC, Intel and Samsung, make the newest kind in volume.

Read it in Transistors and the Front EndAlso in Chip Design, EDA and IP, Photomasks and Pellicles, Who Controls the Chain

Transistor density is how many transistors fit in a square millimeter of chip. SemiAnalysis measured SMIC's N+3 at 113.4 million, against 107.7 million for TSMC's N6. TSMC says N2P gives 1.2 times the logic density and 1.15 times the chip density of N3E. A16, which adds backside power, gives up to 1.10 times the chip density of N2P. TSMC says A14, planned for 2028, will give more than 20 percent more logic density than N2.

Density sets how much logic fits on a die of a given size. No foundry publishes wafer prices, so cost per transistor cannot be worked out from public figures.

Read it in Transistors and the Front EndAlso in Who Controls the Chain

A copper column that runs all the way through a chip so that power and signals can pass from its top face to its bottom face. It makes stacking chips vertically possible, in the way an elevator shaft makes a tall building usable.

High bandwidth memory depends on these columns. US rules control the tools that cut the holes for them, and define those tools by hole shape and etching speed.

Read it in Memory and HBMAlso in Deposition and Etch

A terawatt-hour is a billion kilowatt-hours, the unit national electricity use is counted in. US data centers used 192 TWh in 2024, 4.7 percent of the country's electricity.

Lawrence Berkeley National Laboratory's reference case projects 649 TWh in 2030, 11.8 percent of forecast US electricity use, within a range of 521 to 843 TWh.

Read it in Data Centers and PowerAlso in The Economics of AI Chips

UCIe is an open standard for the short, very fast link between two chiplets sitting side by side in one package. It lets chiplets from different vendors be wired together, the way PCIe lets cards from different vendors share a computer.

Accelerators too large to print as one chip are built from chiplets, and a shared standard lets more firms supply the pieces.

Read it in Chip Design, EDA and IP

In export law a US person is any American citizen, permanent resident or company, wherever in the world they are, and anyone in the United States. Since October 2022 a US person may not service or support an advanced chip fab in China without a license.

The rule reaches people as well as goods, so American citizens, residents and companies need a license to support advanced chipmaking in China.

Read it in Who Controls the ChainAlso in Deposition and Etch, Systems and Networking

Utilization is how full a fab's lines are running, as a share of what they could run. Most of a fab's costs, such as paying off its tools, stay the same whether it runs full or half empty, so utilization largely decides whether it makes money.

SMIC ran its lines 93.5 percent full in 2025, and its gross margin that year was 21 percent.

Read it in Foundries and Fabs

An authorization that BIS, the US Commerce Department office that licenses exports, grants to a named foreign facility, so approved items can ship to it without an individual license each time. The approved facilities are listed in supplement no. 7 to 15 CFR part 748, and the procedure is set out in 15 CFR 748.15.

It let the China subsidiaries of Samsung and SK hynix, and the Dalian NAND flash memory fab that SK hynix bought from Intel, receive US equipment without individual licenses. BIS revoked that status effective 31 December 2025 (90 FR 42321). It said it would license those fabs to keep running, but not to expand capacity or upgrade technology (90 FR 42321). In December 2025 BIS granted SK hynix an annual license to ship approved US equipment to its China fabs during 2026.

Read it in Who Controls the ChainAlso in Deposition and Etch

Vias are the small vertical holes, filled with metal, that connect one layer of wiring to the layer above or below it. A chip's wiring is full of them. An interposer has them through its whole thickness, and a package substrate has them drilled by laser through each sheet of film.

Every added layer brings another set of vias that can fail, so yield falls as packages and substrates grow.

Read it in Advanced PackagingAlso in Deposition and Etch, Memory and HBM

The polished disc of ultrapure silicon that chips are built on, 300 millimeters across for advanced chips. Hundreds of chips are printed on one wafer and cut apart at the end.

A flaw wastes more silicon on a large AI chip than on a small one, so AI chips need wafers that are nearly flawless and flat to the edge. The top five wafer makers hold around 75 percent of a market worth $11.4 billion in 2025.

Read it in Silicon and WafersAlso in Chemicals, Gases and Photoresist, Lithography, Photomasks and Pellicles, Deposition and Etch, Metrology and Inspection, Transistors and the Front End, Foundries and Fabs, Memory and HBM, Advanced Packaging, Test and Assembly, Data Centers and Power, The Economics of AI Chips, Who Controls the Chain

The collective name for the machines that process wafers inside a fab: printing systems, deposition and etch chambers, cleaning tools and measurement systems. It excludes the packaging and test machines used afterward.

Spending on it shows how much new chipmaking capacity is being built. World sales of all chipmaking equipment reached $135.1 billion in 2025, and sales of wafer processing tools rose 12 percent.

Read it in Deposition and EtchAlso in Metrology and Inspection, The Economics of AI Chips, Who Controls the Chain

Wafer sort is the first test a chip gets, while it is still on the wafer. Thousands of needles on a probe card press onto the pads of one die, or of several dies at once, and a tester drives signals in and reads the answers. Any die that answers wrong is marked and never packaged.

Proving a die good before it is packaged keeps one bad die from scrapping the memory stacks and substrate it would be joined to.

Read it in Test and Assembly

Wafers per month is how fab capacity is counted: the number of wafers a plant can start through its line each month. A TSMC gigafab runs more than 100,000. In September 2025 SemiAnalysis conservatively put SMIC's capacity at 7 nm and below at 45,000 a month by the end of 2025. Figures are often converted to 8-inch or 12-inch equivalents so plants with different wafer sizes can be compared.

In June 2024 the industry association SEMI forecast China at 10.1 million wafers a month in 2025, the most of any region. In 2026 it projected China would stay largest through 2027, but little of that capacity is advanced.

Read it in Foundries and FabsAlso in Silicon and Wafers, Deposition and Etch, Advanced Packaging, Who Controls the Chain

Wet chemicals are the liquids a wafer is dipped in or sprayed with between steps: acids that strip a layer, solvents that remove resist, and ultrapure water rinses. Wet processing is any step done in liquid.

CSET's January 2021 brief, drawing on 2019 market reports, put five firms at more than 60 percent of the wet chemicals market. BIS controls wet processing tools by how selectively they etch one material over another.

Read it in Chemicals, Gases and Photoresist

The percentage of chips on a wafer that work. Flaws land at random, so the larger the chip the more likely it is to catch one, and yield falls steeply as chips get bigger.

Yield sets the cost of a working AI chip. Epoch AI models the Blackwell compute die at 40 to 70 percent good, with 60 percent as its central estimate. In the same model, the cost of packages that fail testing, spread across the ones that pass, adds about $1,000 to each B200.

Read it in The Economics of AI ChipsAlso in Deposition and Etch, Metrology and Inspection, Transistors and the Front End, Advanced Packaging, Substrates and PCBs, Who Controls the Chain