The Economics of AI Chips

In December 2025 Epoch AI estimated that building a Blackwell B200 cost about $6,400, and reports in March 2024 put its selling price at $30,000 to $40,000 per chip^[1]. Epoch AI's chip sales model, with data through October 2025, puts Nvidia's compute revenue per GPU in its GB200 rack systems at $33,000 to $42,000, a figure that leaves out the networking gear in those racks^[2]. That $6,400 splits into stages that are expensive because of physics, because capacity is short, or because one firm sets the price.

How it works

Three numbers set the cost of a die, the finished rectangle of circuitry cut out of a wafer.

• Wafer price. TSMC does not publish it. Nvidia makes Blackwell chips on a custom-built TSMC 4NP process^[4]. Epoch AI estimates $17,000 for a 12-inch (300 mm) wafer on that process^[1].
• Dies per wafer. A wafer is a circle and dies are rectangles, so the edge of the disc goes to waste, and the bigger the die, the fewer fit. Each of the two compute dies in a B200 is about 800 mm2^[1]. Nvidia calls them reticle-limited, meaning near the largest a scanner can print in one shot^[4].
• Yield. Defects land at random, so a bigger die is likelier to catch one. Epoch AI models the Blackwell die at 40 to 70 percent good, centered on 60^[1].

Those three numbers put the two dies inside a B200 at about $900 of the roughly $6,400 build^[1]. The estimate counts only variable costs and leaves out fixed costs such as research and development^[1].

Variants and trade-offs

Memory is the largest line

The 192 GB of high-bandwidth memory beside those dies, sold as HBM3E, is the single largest line, about $2,900 at $14 to $17 per gigabyte^[1]. Epoch AI notes that HBM pricing is negotiated individually and can vary significantly by volume and contract length^[1]. The $14 to $17 range dates from December 2025, before the 2026 rise in memory makers' sales and margins described below^[5]. Epoch AI says memory accounts for half of the roughly $6,400 build^[1]. Three firms, SK hynix, Samsung and Micron, dominate the world market for that memory^[3]. SK hynix says demand for its products has exceeded its available supply in recent quarters^[6].

Packaging, substrate and test

CoWoS-L, the TSMC process that mounts dies and memory on one carrier and wires them together, adds about $1,100, more than the logic dies it carries^[1]. Epoch AI models packaging yield at 65 to 95 percent^[1]. A package that fails testing loses its logic dies and memory stacks, and spreading that loss over the good units adds about $1,000 to each B200^[1]. Power delivery hardware, the circuit board, and final assembly and testing add $480^[1]. See Advanced packaging for why packaging capacity runs out first.

The B200 bill of materials

Epoch AI models each line as a range, deriving the packaging line from TSMC's advanced packaging revenue and Nvidia's share of CoWoS capacity^[1]. The estimate covers the accelerator module only and leaves out servers and rack-scale systems^[1]. Epoch AI notes that most Blackwell revenue comes from those systems, which may carry lower margins, so Nvidia's realized margin on Blackwell may be lower than the gap between this cost and the reported chip price suggests^[1].

The B200 is used here because Epoch AI's line-by-line estimate covers it. In its results for the quarter to July 2026, Nvidia said its Vera Rubin platform was ramping into full production^[7]. Each Rubin GPU carries up to 288 GB of HBM4, a newer generation of the stacked memory^[8].

Where the ~$6,400 of B200 manufacturing cost goes, Epoch AI estimate, December 2025$

HBM3E, 192 GB2,900CoWoS-L packaging1,100Packaging yield loss1,000Logic die, two on 4NP900Power delivery, board, test480

Source: Epoch AI B200 cost model, from a $17,000 4NP wafer, 40-70% die yield, $14-17 per GB of memory, and a packaging line derived from TSMC's advanced packaging revenue

From package to rack to cluster

At rack scale the number that matters is the cost of a GPU-hour. For an operator that owns the machine, SemiAnalysis puts a Vera Rubin NVL72 at $3.57, against $1.84 for a GB200 and $2.36 for a GB300^[9]. Each generation costs its owner more per hour than the last, yet SemiAnalysis, working from early CoreWeave results on DeepSeek R1 that it has not verified, finds Rubin cheaper per token than GB200 and GB300 at every interactivity level it compared^[9].

One level up, a 100,000 H100 cluster costs over $4 billion in servers, needs more than 150 MW of data center capacity, uses 1.59 TWh a year, costs $123.9 million a year in power at $0.078 per kWh, and in a rail-optimized design links its GPUs to leaf switches with 98,304 optical transceivers^[10].

Who captures the value

Each figure comes from the firm's own earnings release; for KLA and Ibiden it is gross profit divided by revenue, since those releases give no percentage^{[11][7][12][13][14][15][16][17][18][19]}. For ASE the table shows its packaging and test segment; the company as a whole earned 21.0 percent, because about a third of its revenue came from electronics manufacturing services, which earned 8.9 percent^[18].

SK hynix's earnings release gives no gross margin. Its operating margin was 76 percent in the June quarter, on revenue up 257 percent in a year^[5].

Gross margin, each firm's most recent reported quarter%

Gross margin, each firm's most recent reported quarter

Micron	86.8 %
Nvidia	75 %
TSMC	67.7 %
KLA	61.4 %
ASML	54 %
Lam Research	51.7 %
Applied Materials	50.3 %
Ibiden	36.4 %
ASE packaging and test	27.3 %
Amkor	16.8 %

Source: Each firm's own quarterly earnings release; quarters end between June and September 2026; ASE's bar is its packaging and test segment (TSMC shown)

In the table, design, equipment and leading-edge wafers earn gross margins of 50.3 to 75.0 percent, substrates 36.4 percent, and assembly and test 16.8 to 27.3 percent. In 2026 Micron passed all of them. Its gross margin rose from 39.8 percent for the year to August 2025 to 86.8 percent in the quarter to September 2026^[11]. Nvidia's was 75.0 percent in the quarter to July 2026^[7].

The Semiconductor Industry Association, using monthly data compiled by World Semiconductor Trade Statistics, counted $791.7 billion of global chip sales in 2025^[20]. In its June 2026 forecast, World Semiconductor Trade Statistics put 2025 at $795.6 billion and 2026 at $1.51 trillion, with memory growing about 250 percent and logic 37 percent^[21]. Other totals include $135.1 billion of 2025 equipment billings^[22] and $448.2 billion of 2025 capital spending at Alphabet, Amazon, Meta, Microsoft and Oracle, the sum of Epoch AI's quarterly figures, which Epoch says would reach $770 billion in 2026 if the trend continues^[23]. These totals overlap, so they cannot be added together.

Selected market totals, 2025$B

Selected market totals, 2025

Semiconductor sales	791.7 $B
Hyperscaler capex	448.2 $B
Nvidia data center revenue	193.7 $B
Semiconductor equipment	135.1 $B

Source: Semiconductor Industry Association on chip sales; Epoch AI quarterly capital spending at Alphabet, Amazon, Meta, Microsoft and Oracle, summed for 2025; Nvidia data center revenue for its fiscal year to January 2026; SEMI on equipment billings

Where the money goes

In the B200, packaging and its scrap, $1,100 and $1,000 in Epoch AI's estimate, cost more than twice the $900 of logic dies^[1]. A GB300 NVL72 rack can draw up to 142 kW^[24].

The classes below are a judgment of whether each stage's cost falls as volume grows, drawn from the sources in this chapter and the stage chapters.

Key evaluation criteria

• Cost per good die. The wafer price divided by the dies on that wafer that work. A larger die or a lower yield raises it.
• Memory dollars per gigabyte, and gigabytes per part. The largest line on the bill, set by three firms.
• Packaging yield. Every point lost throws away finished dies and the memory attached to them^[1].
• Share of the bill the vendor does not control. Nvidia sets its own margin but buys memory, packaging and substrates at another firm's price.
• Rack watts. A GB300 NVL72 rack can draw up to 142 kW, and the data center has to supply and cool all of it^[24].
• Compressibility class. Whether the line falls when volume doubles. If it does not, capacity is the constraint.