Deposition and Etch

Applied Materials and Lam Research, the two largest deposition and etch suppliers, booked $28.4 billion and $23.2 billion of revenue in their latest fiscal years^[1][2].

How it works

One round of deposition and etch

1. The wafer. A slice through one spot on a wafer, magnified until its layers show.
2. Deposit. A film a few atoms thick is laid over the whole wafer.
3. Coat. A light-sensitive coating, the resist, is spun on top.
4. Expose. Light shines through a stencil and changes the resist wherever it lands.
5. Develop. A wash removes the resist the light reached, leaving the stencil’s pattern.
6. Etch. A plasma cuts straight down through the film wherever the resist is gone.
7. Strip. The leftover resist is removed. The pattern now sits in the film.
8. Repeat. Insulator fills the gaps and the next layer goes on. A chip takes more than a thousand of these rounds.

Simplified cross-section. The layers are drawn much thicker than they are.

Most etch steps, and many deposition steps, happen in a vacuum chamber that holds one wafer at a time. A pump empties the chamber of air, a measured flow of gas comes in, and an electric field that reverses millions of times a second, a radio-frequency field, turns the gas into a plasma. The field splits the gas into charged ions and into neutral fragments called radicals, which are more reactive than whole molecules^[5]. Batch furnaces such as Tokyo Electron's TELINDY PLUS instead heat as many as 125 wafers at once, usually without plasma, for oxidation, low-pressure chemical vapor deposition and some atomic layer deposition^[6].

For deposition the gas carries the material wanted. The molecules, or the radicals a plasma splits from them, land on the wafer and stick, and the film builds from the bottom up, a few atoms at a time. To coat the floor of a deep hole as thickly as its rim, the machine can work in cycles: let one gas settle in a single layer on every surface, pump it out, admit a second gas that reacts with that layer and nothing else, pump again. Each cycle adds a fraction of a layer of atoms wherever the gas reached, so the film builds up as evenly on the walls and floor of a hole as on its rim^[7].

For etch the gas attacks one material and leaves the one beside it. Wherever the photoresist pattern covers the wafer, nothing happens. Wherever it does not, the radicals react with the surface and turn it into a gas, which the pump carries away. A second field pulls the ions straight down at the wafer, so the etch cuts vertically and a narrow hole keeps its width as it deepens^[5]. When the etch reaches the material underneath, which the gas was chosen not to touch, it slows almost to a stop, and the tool ends the step.

Deposition and etch chambers are separate products built from similar vacuum, gas and radio-frequency parts, and the export controls describe each tool by the process it is designed to run^[7].

A part-finished chip can cross international borders 70 or more times on its way to the end customer, a 2020 estimate by Accenture and the Global Semiconductor Alliance that the Semiconductor Industry Association repeated in 2025^[3].

Variants and trade-offs

Deposition families

The market sizes and leading shares below are CSET's for 2025, which it builds from TechInsights data, on a $26.2 billion deposition tool market^[8] and a $21.9 billion dry etch market^[9].

• Physical vapor deposition knocks atoms off a solid target and lands them on the wafer, $4.9 billion in 2025^[10].
• Chemical vapor deposition reacts gases at the wafer surface to grow a film; the plasma-enhanced version runs cooler and is most of the $11.2 billion CVD market, $7.5 billion in 2025^[11][12].
• Atomic layer deposition lays down less than one atomic layer at a time, so it coats vertical walls as evenly as horizontal floors. US regulators call it a 3D scaling enabler in 3D DRAM, 3D NAND, and FinFET and gate-all-around logic^[7]; ASM International leads it with 54.5 percent of a $4.1 billion market in 2025^[13].
• Epitaxy grows layers that line up with the crystal beneath them, using high-temperature CVD tools^[14]. Electroplating deposits the copper used for wiring across the wafer^[15].

Etch families

• Conductor etch cuts gates, metals and silicon, $12.2 billion in 2025, led by Lam at 51.2 percent^[16].
• Dielectric etch cuts the insulating oxides and nitrides between them, $8.7 billion in 2025, led by Tokyo Electron at 55.9 percent^[17].
• High-aspect-ratio etch cuts the deep, narrow channels that let 3D NAND stack layers of memory cells, and Lam says slight deviations from the target profile can hurt yield^[4]. Lam runs the etch well below 0 degrees Celsius and says Cryo 3.0 holds critical-dimension deviation under 0.1 percent down channels up to 10 microns deep^[4].

AI hardware asks for sideways cuts, deeper holes and a second metal stack on the wafer's back.

• Gate-all-around needs highly selective isotropic etch, which cuts sideways, and BIS controls isotropic dry etch tools with a silicon-germanium-to-silicon selectivity of 100:1 or more^[7].
• HBM needs holes etched straight through the silicon so chips can be stacked and wired, which BIS controls at 10:1 or deeper above 7 microns a minute^[18].
• Backside power delivery moves power routing to the back of the wafer^[19]. Applied Materials expects it to add another $1 billion per 100,000 wafer starts a month to the wiring market it serves^[20].

Tokyo Electron world market share by tool type, 2025%

Tokyo Electron world market share by tool type, 2025

Coater/developer	91 %
Tube and low-pressure CVD	38 %
Oxidation/diffusion	31 %
Deposition (furnace, ALD, LPCVD)	27 %
Dry etch	23 %
Cleaning	20 %
ALD	15 %

Source: Tokyo Electron FY2026 Q4 results presentation

Who makes it

SEMI put global equipment billings at $135.1 billion in 2025, up 15 percent from $117.1 billion, with wafer processing equipment up 12 percent^[22].

Within deposition and etch no one firm dominates as ASML does in lithography. The share chart in Tokyo Electron's own results presentation puts it at 23 percent of dry etch, 27 percent of deposition systems (furnace, ALD and low-pressure CVD tools) and 15 percent of ALD in 2025, against 91 percent of coater/developer^[21].

ASM International, the atomic layer deposition specialist, reached a record EUR 3.2 billion of revenue in 2025 as customers built 2 nm gate-all-around capacity, with molybdenum ALD entering volume production^[23].

What the world spent on chipmaking equipment$B

What the world spent on chipmaking equipment

2024	117.1 $B
2025	135.1 $B

Source: SEMI, Worldwide Semiconductor Equipment Market Statistics

China and the controls

China is the tool vendors' largest market, and Chinese toolmakers have gained share since 2019^[24]. It bought $49.3 billion of equipment in 2025, still the biggest single market, though its spending fell half a percent while Taiwan's rose 90 percent to $31.5 billion^[22]. China still takes a large share of every major vendor's sales.

• Tokyo Electron: 34.1 percent of sales in the year to March 2026, down from 41.7 percent^[21].
• Lam Research: 26 percent in the June 2026 quarter, behind Taiwan at 27 percent^[2].
• Applied Materials: 28 percent in the third fiscal quarter of 2026, down from 35 percent^[25].
• ASM International: more than 30 percent of 2025 revenue^[23].

Between 2019 and 2024 China-based suppliers went from 2 to 7 percent of deposition and from under 3 to almost 9 percent of etch and clean, and in ALD they gained no share and held less than 1 percent in 2024^[24]. CSET's newer analysis of TechInsights data published in July 2026 puts them at 9.8 percent of deposition in 2025^[8]. They held 10.1 percent of etch and clean that year^[26]. In dry etch alone their share was 12.4 percent^[9]. In ALD they held 2.6 percent in 2025, most of it from Piotech^[13]. AMEC by itself held 12.4 percent of dielectric etch in 2025^[17]. AMEC turned over RMB 12.385 billion in 2025, up 36.6 percent, and spent RMB 3.744 billion on research, 30.2 percent of sales^[27].

Washington tightened these rules at least five times between 2022 and 2025.

• October 2022. The 7 October interim final rule put certain chipmaking equipment and some US person support under license and widened foreign-produced item rules for 28 listed Chinese entities^[28].
• October 2023. The rule effective 17 November rewrote the equipment entries, adding isotropic and anisotropic dry etch (ECCN 3B001.c.1), spatial ALD (3B001.d.9), low-fluorine tungsten ALD and CVD (3B001.d.10) and carbon hard mask PECVD (3B001.d.5)^[7].
• December 2024. BIS controlled 24 more types of equipment and three types of software, added 140 entities and wrote a foreign direct product rule that reaches some tools built outside the United States^[29]. The new entries take in TSV etch and deposition into features with aspect ratios above 200:1^[18]. The rule largely exempts foreign-made tools exported by firms located in Japan, the Netherlands and the 31 other countries it lists, whose governments can control these tools themselves^[18]. Japan added advanced chipmaking equipment to its control list on 23 July 2023^[18].
• September 2025. BIS removed the Chinese units of Samsung and SK hynix, and Intel Semiconductor (Dalian), from the Validated End-User program, effective 31 December 2025, so US tools bound for them now need a license^[30]. BIS estimated that the change would add 1,000 license applications a year^[30].
• September 2025. The Affiliates Rule extended Entity List restrictions to any company at least 50 percent owned by a listed entity^[31]; BIS then stayed it to 9 November 2026^[32].

Applied Materials took a $253 million charge to settle an export controls compliance matter with BIS, so the rules reach the vendors as well as their customers^[25].

Of the tools in the chart below, China's share is largest in dry stripping, a $314.6 million market in 2025, where Mattson Technology held 22.6 percent and Naura 8.3 percent^[33]. Mattson is a US-based firm that Beijing E-Town bought in 2016^[24].

China-based suppliers' share of global tool segments, 2025%

China-based suppliers' share of global tool segments, 2025

Dry strip (mostly Mattson)	31 %
PVD	14.7 %
Dielectric etch	13.4 %
Dry etch	12.4 %
Etch and clean	10.1 %
Deposition	9.8 %
CVD	8.8 %
Lithography (i-line)	4.2 %
ALD	2.6 %

Source: CSET analysis of TechInsights data (published July 2026), ETO Chip Explorer

The chokepoint

The chokepoint is real but weaker than lithography's. Three or four credible vendors exist for most deposition and etch steps, and atomic layer deposition has at least five, led by ASM International at 54.5 percent in 2025^[13]. China's own toolmakers held only 2.6 percent of atomic layer deposition in 2025^[13]. The December 2024 rule targets advanced atomic layer deposition tools and the extremely deep, narrow holes that HBM and 3D memory need^[18].

Key evaluation criteria

• Selectivity. How hard the process attacks one material and spares another. BIS controls wet processing at a silicon-germanium-to-silicon ratio of 100:1^[7].
• Conformality and aspect ratio. Whether a film reaches the bottom of a hole, and how deep that hole is against its width. Controls start at 10:1 for TSV etch and 200:1 for 3D DRAM deposition^[18].
• Uniformity. Variation across a 300 mm wafer, with the TSV etch control set at within-wafer etch depth nonuniformity of 2 percent or less^[18].
• Throughput. Wafers per hour, which sets cost per layer and decides how many lots a fab can run.
• Particles and chamber matching. How large a share of the defects a fab can tolerate comes from these tools, and whether one chamber behaves like the next, which metrology and inspection measure (see Metrology and inspection).