Silicon and Wafers

The whole world market for silicon wafers came to $11.4 billion of revenue on 12,973 million square inches in 2025^[1]. That is a small fraction of Nvidia's data center revenue, which reached $193.7 billion in the fiscal year to January 25, 2026^[2].

How it works

From sand to wafer

1. Refine. Silicon starts as sand and rock. It is refined into rods so pure that, of every hundred billion atoms, fewer than one is anything else.
2. Grow. The rods are melted. A seed crystal touches the melt and is drawn slowly up, turning, and the silicon freezes onto it as one long crystal.
3. Slice. A wire saw slices the crystal, called an ingot, into thin discs.
4. Polish. Each disc is ground, etched and polished until it is flat to within a few atoms, right out to the edge.

Simplified. The ingot and the machines are not drawn to scale.

Silicon starts as quartzite, a rock that is silicon bound to oxygen. An arc furnace melts it with carbon, and the carbon takes the oxygen away as gas, leaving rough silicon metal. Refiners turn the metal into a gas, trichlorosilane, and distill it, because the impurities boil at other temperatures and stay behind. The clean gas then flows over silicon filaments heated inside a bell jar. On the hot surface the gas breaks apart, its silicon settles onto the filaments, and over days the filaments thicken into gray rods of polysilicon, the Siemens process. Everything downstream is made from those rods. Polysilicon comes in two ultra-high-purity grades, one for semiconductors and one for solar cells, and chips use the semiconductor grade^[5].

A grower melts the polysilicon at about 1,420 degrees Celsius, hotter than lava, and pulls a single crystal out of it by the Czochralski method^[3]. The grower lowers a small seed crystal on the end of a rod to the surface of the melt and draws it back up, slowly turning. Silicon freezes onto the seed in the seed's own atomic pattern, and a cylinder grows beneath it, the ingot. The pull starts with a thin neck so that the flaws formed where the seed first touched the melt end in the neck and never reach the ingot. Boron or phosphorus stirred into the melt, a step called doping, sets how readily the wafer conducts and whether the current in it is carried by negative charges or positive ones.

A wire saw, a web of fine wire running through abrasive, slices the ingot into discs. The maker then laps each disc, grinding both faces flat between rotating plates, chemically etches off the damaged surface, and polishes it to a mirror with colloidal silica, a slurry of silica particles far too small to see. Epitaxial wafers get one more layer of near-perfect silicon grown on top at about 1,200 degrees Celsius^[3], still hot enough to glow orange, and almost every step throws material away.

Variants and trade-offs

Polished versus epitaxial

A polished wafer is a doped single crystal polished to a mirror finish^[3]. An epitaxial wafer is a polished wafer with a thin layer of single-crystal silicon grown on top at about 1,200 degrees Celsius^[3]. The transistors live in that layer, so its quality sets the lowest leakage the chip can reach and its risk of latch-up, a parasitic short between power and ground. SEMI, the industry association, credits the 2025 rise in shipments to AI-driven demand for advanced epitaxial wafers in logic and polished wafers for high-bandwidth memory^[1].

Silicon on insulator

A buried layer of oxide, which is glass, separates a thin working layer of silicon from the bulk beneath, and Soitec's Smart Cut process makes nearly all of it^[6]. Soitec's SOI product lines include RF-SOI for radio chips and FD-SOI, and its markets run from mobile communications to cloud AI^[6]. SEMI tied the AI-driven growth in logic to advanced epitaxial wafers^[1].

Who makes it

In a January 2021 brief, CSET at Georgetown named Shin-Etsu, SUMCO, GlobalWafers, Siltronic and SK Siltron, headquartered in Japan, Taiwan, Germany and South Korea, as key wafer firms^[7]. It also listed nine Chinese-owned producers, among them Zhonghuan, Simgui, ZingSEMI and Finland's Okmetic, but said they generated little revenue in comparison^[7]. As of 2018, five Chinese firms were making or planning 300 mm wafers^[7]. Eswin's October 2025 listing prospectus counts seven Chinese firms, Eswin included, making 300 mm wafers at scale, with a combined capacity of 2.94 million wafers a month at the end of 2024^[8].

Silicon wafer sales by supplier headquarters, 2023. Japan held 53%, and the source shows no separate share for China or the United States%

Japan53%Taiwan19%South Korea13%Europe10%Other5%

Source: METI, December 2025, from Fuji Keizai data (2023); Japan's share is printed, the others are read off METI's chart

The chart shows shares of 2023 sales from a survey by Fuji Keizai, a Japanese research firm, relayed in the December 2025 strategy deck of Japan's Ministry of Economy, Trade and Industry^[9]. The deck prints only Japan's 53 percent, so the other shares are read off its chart, which gives no separate share to Chinese or US companies^[9]. Siltronic's April 2026 investor presentation says the top five wafer makers serve around 75 percent of the market, based on revenue in the first three quarters of 2025^[4].

Their 2025 results split between an AI boom and a slump in the older, mature nodes.

• Shin-Etsu. Its parent's electronics materials segment sold ¥1,015.7 billion in the year to March 2026, up 9 percent, as AI-related demand stayed strong and demand in other sectors began to rise, lifting sales of silicon wafers, photoresist and photomask blanks^[10]. The segment also sells rare earth magnets and other materials, and the results release does not break out wafer sales, so the figure cannot be compared with the wafer revenue of the other firms here^[10].
• SUMCO. Sold ¥409.7 billion and still lost ¥11.8 billion, as operating profit fell from ¥36.9 billion to ¥1.3 billion while it added leading-edge 300 mm capacity and reorganized production of 200 mm and smaller wafers, where demand stayed weak^[11].
• Siltronic. Lost €77.9 million on €1,346.7 million of sales while investing €369.1 million, with its new Singapore fab as the focus^[12].
• GlobalWafers. NT$60.6 billion of revenue, down 3.24 percent in local currency^[13].

Area shipped rose 5.8 percent in 2025 while revenue fell 1.2 percent^[1]. SEMI attributes the softer revenue mostly to traditional chip applications, where demand and pricing had yet to improve^[1].

China made 1.50 million metric tons of polysilicon, the raw material, in 2023, about 93 percent of world output^[14]. Solar-grade material was an estimated 98 percent of that output and electronic-grade 2 percent^[14]. The Commerce Department found in 2026 that semiconductor-grade polysilicon makes up only 2.4 percent of global production, a split close to China's^[15]. The share alone does not show whether Chinese polysilicon goes into chips.

China's polysilicon output by grade, 2023. China made 1.50 million metric tons that year, about 93% of world output%

Solar-grade98%Electronic-grade2%

Source: USGS Minerals Yearbook, China, 2023

Siltronic put the 2025 market for electronic-grade silicon at $1.4 billion, with five major suppliers, none of them Chinese: Wacker, Hemlock, OCI, Tokuyama and Mitsubishi^[4].

The leading wafer makers are headquartered in Japan, Taiwan, Germany and South Korea, and Siltronic of Germany describes itself as the only Western-based maker among the top five, based on revenue in the first three quarters of 2025^[4]. GlobalWafers opened a $3.5 billion plant in Sherman, Texas in May 2025, the first production line of its kind built in the United States in over twenty years, and announced another $4 billion for phases three and four the same day^[16]. Washington had awarded it up to $406 million under the CHIPS incentives program for wafer plants in Texas and Missouri^[17].

Presidential Proclamation 11052, signed August 6, 2026, sets a minimum import price of $100 per kilogram for polysilicon ingots and wafers and an extra 15 percent duty on imported ingots and other listed products made from polysilicon, both from December 4, 2026^[15]. A September 2026 Commerce rule meant to stop stockpiling before the duties start lists tariff code 3818.00.0040 among the products it covers^[18]. That code covers round, doped, single-crystal silicon wafers^[19]. Commerce may approve plans to build US polysilicon, ingot, wafer or cell plants whose construction starts by January 20, 2029, and firms with approved plans can import equipment and some of those products without the new duties^[15].

The chokepoint

China dominates polysilicon, and in 2019 it had almost no share in wafers. As of 2019 Chinese firms held under 5 percent of the wafer market and under 1 percent of 300 mm^[7]. As of 2018, Chinese producers made 12 percent of the wafers for Chinese-headquartered 300 mm fabs, against 18 percent for 100 to 200 mm fabs^[7]. Eswin, mainland China's largest maker of 300 mm wafers, says it ranked sixth in the world with about 7.7 percent of global 300 mm shipments in the first half of 2026^[20]. Its October 2025 Shanghai listing prospectus, drawing on SEMI data, estimates that the five largest makers shipped about 79 percent of 300 mm wafers in 2024, Eswin about 6 percent and all other makers about 15 percent^[8].

Making the smoothest, high-purity 300 mm wafers takes considerable know-how that is hard to write down, and 300 mm carried 99.7 percent of world fab capacity at 45 nm and below in SEMI figures from November 2020 cited by CSET^[7]. Counting wafers of every size, SEMI estimated that 300 mm wafers made up about 78.8 percent of the wafer area shipped worldwide in 2025, according to Eswin's 2025 annual report summary^[21]. Customers have to qualify a new wafer plant before they buy from it, and Siltronic completed key customer qualifications at its new Singapore fab in July 2025^[4].

The last increase in wafer size, to 300 mm, happened in 2002^[7]. Bigger discs make printing a bigger share of the processing cost, and a 2013 University of Texas lecture cited by CSET put photolithography at half the cost of processing a 300 mm wafer against a quarter of a 150 mm one^[7]. Wafers are still produced in diameters of up to 300 mm^[1].

One fatal defect ruins far more silicon on a GPU die that fills a whole printed field than on a small chip, and extreme-ultraviolet printing stays in focus over only a very small range of heights (see Lithography), so flatness has to hold at every point on the disc.

Key evaluation criteria

• Grade. Chips need electronic-grade polysilicon, and none of the five major suppliers of it that Siltronic named for 2025 is Chinese^[4].
• Defect density in the epitaxial layer. A big AI die loses more good silicon per defect than a small chip does, and SEMI's wafer group says the move to sub-3nm processes is raising requirements for wafer quality and consistency^[1].
• Flatness and nanotopography, the fine ripple across the surface, because extreme-ultraviolet exposure stays in focus over only a very small range of heights, and that has to hold across a 300 mm wafer.
• Diameter, where 300 mm carried 99.7 percent of world fab capacity at 45 nm and below in SEMI figures from November 2020 cited by CSET^[7]. Of all the wafer area shipped worldwide in 2025, 300 mm wafers made up an estimated 78.8 percent^[21].
• Contract structure, since Siltronic expects continued price pressure in 2026 on sales outside its existing long-term agreements^[12].