Advanced Packaging

A lithography scanner prints a rectangle 26 mm by 33 mm, or 858 mm2, in one exposure^[1]. Every AI accelerator worth buying is bigger than that. Packaging is the stage that lets an accelerator be larger than that rectangle, and it decides how much larger.

How it works

High bandwidth memory gives a second reason for the interposer. An HBM4 stack connects through 2,048 data signals, packed too tightly for a standard resin base board, so the memory sits beside the logic on that shared carrier, the interposer^[2]. Even Nvidia's H100, whose single logic die is 814 mm2 and fits inside one exposure, carries five HBM stacks^[3]. Epoch AI counts CoWoS packaging among the three inputs the H100 needs, along with its logic die and its HBM^[4].

The parts of an AI accelerator

1. Package base. An AI chip is built from several parts. First comes the package base, a layered board that connects everything to the circuit board below.
2. Silicon base. On it sits a thin slab of silicon, called an interposer. Its fine wiring joins everything placed on top.
3. Logic chips. Two logic chips go in the middle. They do the calculating, and each is as large as a chipmaking machine can print.
4. Memory. Eight stacks of memory go beside them, a few millimeters away. They hold the AI model’s weights and the record of each conversation so far.
5. One package. Together they make one AI accelerator. Nearly every one is put together by TSMC, in Taiwan.

Simplified view of a two-die, eight-stack accelerator. Footprints follow the sizes in this chapter and chapter 10; heights are exaggerated so each layer shows.

The name CoWoS says the order: chip onto wafer, then wafer onto substrate. For CoWoS-S, TSMC makes a thin silicon wafer carrying wiring and vertical copper vias, metal-filled holes that join one layer of wiring to the next, but no transistors. It bonds the logic dies and memory stacks face down onto that wafer with microbumps, dots of solder 30 to 40 microns apart, about a third of a hair's width, each dot one electrical joint. Then it cuts the interposer out of the wafer, attaches it to the resin substrate, and the substrate goes onto its board.

Each of those packaging steps is ordinary on its own. But one cracked joint scraps a package holding eight qualified HBM stacks and two large, expensive logic dies.

Variants and trade-offs

2.5D: silicon, RDL and bridges

TSMC has run CoWoS in volume since 2012^[5]. CoWoS-S wires most finely, but its interposer is one unbroken piece of silicon whose yield falls as the area grows. CoWoS-L replaces that slab with an interposer of redistribution wiring and small embedded silicon bridges where the wiring is densest^[6]. Intel's EMIB buries the same bridge idea in the resin substrate, and SemiAnalysis reported in March 2026 that Trainium and TPU were adopting it to different degrees^[7].

Blackwell was the first high-volume design on CoWoS-L, and packaging issues at TSMC and in Nvidia's design limited its supply^[8]. The bridges carrying the 10 TB/s link between the two compute dies need very high placement accuracy, and the different expansion rates of the dies, bridges, interposer and substrate caused warpage^[8].

3D: SoIC and Foveros

TSMC's SoIC and Intel's Foveros bond dies face to face, copper pad to copper pad with no solder, packing the connections far closer than microbumps allow. TSMC put 3 nm SoIC into volume production in 2025^[6]. An A14-on-A14 version due in 2029 will carry 1.8 times the die-to-die connection density of the 2 nm version^[9]. Heat decides the layout: the bottom die overheats and the top is hard to power, so 3D designs often put cache underneath and compute on top.

The same bonding brings optics into the package. TSMC's COUPE uses SoIC to join a silicon photonics chip, which sends data as light, to its electrical control chip^[6]. TSMC said in April 2026 that COUPE on substrate would begin production in 2026, and that placing this optical engine inside the package gives twice the power efficiency of a pluggable version on the circuit board^[9].

Two ways off the silicon interposer

Panel-level packaging swaps the round wafer for a rectangular panel and wastes far less area; see Test and assembly. JEDEC published SPHBM4 on 13 July 2026. It puts HBM4 memory on a base chip carrying 512 data signals instead of 2,048, which spaces the connections widely enough to mount the stack on a standard resin substrate, off the silicon interposer altogether^[2].

Capacity

TSMC does not publicly disclose its CoWoS capacity^[4]. Industry estimates from SemiWiki and TrendForce, compiled by Epoch AI, put it at about 65,000 to 75,000 wafers a month at the end of 2025, up from 35,000 to 40,000 a year earlier^[4]. At its 2024 symposium TSMC said capacity would grow at a 60 percent compound annual rate over the next few years, but when asked about that rate on the July 2024 earnings call, C.C. Wei said only that he would keep adding capacity wherever he could and could not yet balance supply and demand^[10].

In October 2025 Wei would still say only that TSMC was working to increase capacity in 2026 and would probably give the real number in 2026, and that front-end and back-end capacity were both, in his words, very tight^[11].

Epoch AI weighs each designer's component use against world supply and puts Nvidia at 60.3 percent of all CoWoS in 2025, with a 90 percent confidence interval of 56.5 to 64.3; Google took 13.5, AMD 8.4 and Amazon 7.4^[4]. Those four consumed around 90 percent of global CoWoS capacity and HBM supply, with HBM measured by value, while consuming only 12 percent of advanced logic die production^[4].

Estimated share of CoWoS capacity used, 2025%

Nvidia60.3%Google13.5%AMD8.4%Amazon7.4%Everyone else10.4%

Source: Epoch AI, advanced packaging and HBM were the bottlenecks on AI chip production in 2025

In March 2026, one analyst firm, SemiAnalysis, judged that front-end capacity had become the dominant bottleneck and CoWoS constraints were easing, and that TSMC was planning CoWoS capacity around its N3 limits because added packaging capacity is of no use without front-end wafers to fill it^[7].

TSMC gave a different account four months later. On the July 2026 earnings call, Wei said its packaging capacity was so tight that it limited customers' growth, and that back-end capacity was still in shortage^[12]. Asked about Intel's EMIB-T, he said he welcomed the extra flexibility and hoped it would take some of the load off TSMC^[12].

Who makes it

CoWoS interposer size on TSMC's roadmapreticles

CoWoS interposer size on TSMC's roadmap

2024, CoWoS-L	3.5 reticles
2026, in production	5.5 reticles
In development	9.5 reticles
2028	14 reticles

Source: TSMC 2025 annual report and 2026 technology symposium

The word packaging covers three kinds of firm. TSMC, which makes chips for others, and Intel, which makes its own, package chips in their own back-end fabs, and outsourced assembly and test firms do the rest. Intel opened Fab 9 in Rio Rancho, New Mexico, in January 2024 to make its Foveros 3D packages in volume, and called it the only US factory producing the most advanced packaging at scale^[13]. ASE Technology Holding, the leading provider of assembly and test services, billed NT$645.4 billion in 2025, about 40 percent of it from electronics manufacturing services^[14]. Its assembly, test and materials business brought in NT$389.2 billion, up from NT$325.9 billion in 2024^[14]. Amkor, the world's largest US-headquartered one, billed $6.71 billion^[15].

The tools are a narrower chokepoint than the assembly houses.

• Thermocompression bonding. Pressing dies together under heat and force. ASMPT's advanced packaging revenue reached $532.1 million in 2025, with thermocompression bonder revenue up about 146 percent; it targets 35 to 40 percent of a market it puts at $1.6 billion in 2028^[16].
• Hybrid bonding. Solder disappears and copper pads meet directly. Applied Materials co-developed its Kinex hybrid bonding system with Besi, which Applied calls the industry leader in hybrid bonding^[17].
• Grinding and dicing. Disco held 87 percent of the $1.9 billion world market for dicing tools in 2025, a category that covers the grinders that thin wafers and the saws that cut them into chips, by CSET's count from TechInsights data; see Test and assembly^[18].

TSMC's Arizona commitment reached $265 billion in July 2026 and covers two advanced packaging plants alongside 10 fabs^[19]. Amkor started building a $7 billion campus in Peoria in October 2025 and expects production from early 2028^[20]. The Commerce Department awarded Amkor up to $407 million in CHIPS Act funding for the site in December 2024^[21]. In October 2025 Wei said a large outsourced packaging partner already breaking ground in Arizona was on an earlier schedule than TSMC's own two packaging fabs there^[11].

The chokepoint

China-based suppliers' share of selected tool segments, 2024%

China-based suppliers' share of selected tool segments, 2024

Test, linear and discrete	69 %
Burn-in test	9 %
Advanced packaging fabrication tools	7 %
SoC test	5 %

Source: CSET, Inside Beijing’s Chipmaking Offensive

JCET, a leading Chinese assembler, billed a record RMB 38.87 billion in 2025, up 8.1 percent^[23]. Between 2019 and 2024, Chinese firms gained 5 percentage points of share in test tools and 4 points in fabrication tools built for advanced packaging, but lost share in bonding and other conventional assembly and packaging tools, the category where CSET counts hybrid and thermocompression bonders^[22]. Within those advanced packaging fabrication tools, China gained 10 points in etch and clean tools and 3 points in deposition tools, and lost 2 points each in lithography and CMP tools^[22]. In 2024 China held 7 percent of advanced packaging fabrication tools, against 65 percent for the United States and 15 percent for Japan^[22]. Four of the top ten outsourced assembly and test firms by 2024 revenue are headquartered in China^[22]. JCET says its XDFOI platform has entered high-volume manufacturing with redistribution-layer interposer, silicon interposer and silicon bridge options^[24].

Each generation on TSMC's roadmap needs a larger interposer.

• 2028. A 14-reticle interposer carrying about ten large compute dies and 20 HBM stacks, roughly 12,000 mm2 of interposer, about the area of a compact disc^[9].
• 2029. More than 14 reticles, and a 40-reticle System-on-Wafer beside it^[9].

Key evaluation criteria

• Interposer area is the limit on how much logic and memory fit, now 5.5x reticle on CoWoS-L^[9].
• Package yield decides whether a generation ships on time, and nobody publishes it.
• Warpage control covers the expansion mismatch between die, bridge, interposer and substrate that caused warpage in Blackwell, the first high-volume CoWoS-L design^[8].
• HBM stacks supported is about 20 on the 14-reticle package due in 2028^[9].
• Bonder throughput depends on the toolmakers, and ASMPT alone targets 35 to 40 percent of the thermocompression bonding market^[16].
• Substrate size limits everything above it. A 14-reticle interposer needs a resin substrate that will not warp under it, which pushes ABF build-up film to its limits; see Substrates and PCBs.