Chip Design, EDA and IP

Design is the only stage in this chain without a factory, and one the US government has already restricted by letter. In late May 2025 the US government required a license to sell chip design software to anyone in China, and Cadence cut off its Chinese customers until the rule was lifted on 2 July^[1].

How it works

How a chip is designed

1. A blueprint. Making a chip starts with design, which turns an idea into a complete blueprint. The blueprint fixes where each of the chip’s billions of switches sits and how each one is wired to the others.
2. One tick. The chip works in ticks, each less than a billionth of a second. On every tick a signal leaves a register, a small store that holds one number, and it has to cross its wire to the next register before the next tick.
3. Too far. If the next register sits far away, the wire is long. The signal is still on its way when the next tick comes, so it arrives too late.
4. Placed closer. Design software from three companies, Synopsys, Cadence and Siemens, places the parts and wires them together. Here it moves the register closer, and the signal arrives in time.
5. Checked. The software checks that every signal on the chip arrives in time, and a chip factory accepts only designs that pass. The factory then prints the blueprint onto silicon through stencils, and changing it after that costs new stencils and several months.

Simplified. Not to scale. The floorplan follows a GPU die; one tick, less than a billionth of a second, is slowed to about two seconds.

Design runs in five stages, each one's output the next one's input, all of it in software.

• Architecture. Engineers fix the shape of the chip: how wide the block that multiplies numbers is, how much fast on-chip memory sits beside it, how many high-bandwidth memory stacks line the edges. The output is a plan.
• RTL. Engineers write the plan as register-transfer-level code, RTL, in the hardware language SystemVerilog. A register is a small store on the chip that holds one number, and the clock is the tick that moves every register forward together. The code says what every register holds on every tick, and the output is a text description of the whole chip.
• Verification. A large team checks that the code does what the plan says. They run it in simulation, prove parts of it correct with mathematics, and load it into emulators, cabinets of reprogrammable chips that behave like the design, so the chip's own software can boot before any silicon exists.
• Physical design. Software swaps each piece of the code for a logic cell, a small ready-made circuit the foundry has already proved it can make, then places the cells on the chip, wires them together and proves that every signal arrives in time.
• Tape-out. The handover. Software turns the placed layout into pattern files for the mask shop. First it pre-distorts each shape so that it prints as drawn, which is optical proximity correction; then it cuts the layout into the files a mask writer reads, which is mask data preparation.

All that checking exists because each revision after tape-out needs at least some new masks^[2]. In 2022 SemiAnalysis put a full set at more than $1 million at 28 nm and more than $10 million at 7 nm, and expected 3 nm sets to push into the $40 million range^[2]. Its May 2026 primer still puts a leading-edge mask set at $40 million, and a single respin, a revision after tape-out, at leading-edge nodes at $50 million to $100 million^[3]. In 2022 SemiAnalysis also reported that startups had taken chips on TSMC 7 nm, then a leading-edge process, from design to tape-out for $50 million to $75 million, everything included^[2]. In September 2026 CSIS put a different measure, the cost of developing a leading-edge 2 nm chip, at about $725 million, against $48 million to develop a 28 nm design in the late 2000s^[4]. The nanometer labels name generations of the process, each finer than the last, and no longer measure anything.

What one photomask set costs, by node, 2022 ($M). The 28 nm and 7 nm figures are minimums$M

What one photomask set costs, by node, 2022 ($M). The 28 nm and 7 nm figures are minimums

28 nm	1 $M
7 nm	10 $M
3 nm	40 $M

Source: SemiAnalysis, The Dark Side of the Semiconductor Design Renaissance, July 2022. The 3 nm figure was a 2022 forecast. SemiAnalysis's May 2026 EDA Market Primer puts a leading-edge mask set at $40M

Variants and trade-offs

Merchant GPU versus custom ASIC

Nvidia designs Blackwell once and sells it to everyone, so the buyer gets mature software and a resale market. A custom accelerator, an ASIC built for one company's own workload, is narrower and tuned to that one workload. Google's seventh-generation tensor processing unit, Ironwood, carries 192 GB of memory per chip, six times its predecessor's, and delivers twice the performance per watt^[5].

The EDA flow

Three complete flows exist, and a change of synthesis tool means re-running place-and-route, signoff and physical verification^[3]. Foundries also specify which signoff tools their customers must use for tape-out^[3]. Synopsys alone holds more than 90 percent of static timing analysis, the check that proves a chip will run at its rated speed^[3], so inside some steps of the flow one vendor holds most of the market.

Each leading vendor's share of its own design-software segment. Lower end of each reported range%

Each leading vendor's share of its own design-software segment. Lower end of each reported range

Static timing (Synopsys PrimeTime)	90 %
Physical verification (Siemens Calibre)	85 %
Synthesis (Synopsys Design Compiler)	84 %
Emulation (Cadence Palladium)	55 %

Source: SemiAnalysis, EDA Market Primer, May 2026

Buy the IP or build it

Design houses license the processor cores, the interface controllers and the blocks that drive high-bandwidth memory. Arm licenses processor designs, and in fiscal 2026 it reported $4.92 billion of revenue, $2.61 billion of it royalties, and said it held about 50 percent of processor compute at the top cloud firms^[6]. In 2026 Arm also launched the Arm AGI CPU, its first production silicon product, and by May 2026 servers built on it could be ordered from ASRock, Lenovo, Quanta and Supermicro^[6]. The memory interface is a demanding block, because it has to hold its timing across thousands of microscopic solder bumps into a stacked memory die. RISC-V, the open instruction set that needs no license, handles the small control tasks on the chip, and Nvidia now uses it in every GPU^[7].

Chiplets

The reticle limit, the largest area a scanner can print in one exposure, limits how large a single die can grow^[8]. Many large accelerators are built from chiplets, several smaller dies wired together, and UCIe is an open industry standard for the links between them inside a package^[9]. Version 3.0 of UCIe adds 48 and 64 GT/s data rates^[9]. Broadcom's 3.5D XDSiP platform packs more than 6,000 mm2 of silicon and 12 high-bandwidth memory stacks into one package^[8].

Who makes it

Design software and licensed blocks were an $18 billion market in 2025, and Synopsys, Cadence and Siemens EDA took more than 85 percent of it, counting Ansys as part of Synopsys, with no other vendor above 5 percent in any core category^[3].

Synopsys is the largest. Its own results put revenue at $7.054 billion for the fiscal year to 31 October 2025, with Ansys, bought that July, contributing $756.6 million^[10]. Cadence, whose year ends in December, took $5.297 billion in calendar 2025^[11]. The two fiscal years do not line up, so any total for this market depends on which twelve months are counted and on how much of Ansys it includes. SemiAnalysis counts Synopsys at $8 billion for calendar 2025 with Ansys included, and it puts 31 percent of Ansys's business in semiconductors and high technology, 22 percent in aerospace and 18 percent in automotive^[3].

Design software and licensed-block revenue share, 2025. Synopsys includes Ansys%

Synopsys44%Cadence29%Siemens EDA13%All others13%

Source: SemiAnalysis, EDA Market Primer, May 2026. Shares calculated from its calendar 2025 revenue figures, with Synopsys at $8B including Ansys and Siemens EDA at the middle of its $2.2-2.5B estimate

Some chip firms also build custom accelerators to a customer's design and sell the finished chips. Broadcom booked $16.7 billion of AI semiconductor revenue in the third quarter of fiscal 2026, up 221 percent year over year, a figure that covers both its custom AI accelerators and its AI networking chips^[12].

In October 2025 OpenAI and Broadcom said they would deploy 10 gigawatts of OpenAI-designed accelerators, with Broadcom turning the design into silicon and supplying the Ethernet networking around it^[13]. In April 2026 Broadcom extended its Meta partnership to multiple gigawatts of MTIA, Meta's in-house chip, and the first 2 nm AI accelerator^[14].

Below Broadcom and Marvell sit the Taiwanese design-service houses that carry a customer's circuit list all the way to a finished mask set on TSMC's newest nodes; Alchip reported $992 million of revenue in 2025^[15]. The engineers are spread across more countries than the firms, and India alone holds nearly 20 percent of the world's chip designers^[16].

The chokepoint

A narrower control came first. Since 14 October 2022, design software specially made for chips with gate-all-around transistors, a design the rule calls key to processes at 3 nm and below, has needed a US export license for national-security reasons^[17]. That license requirement covers exports to China^[18]. The control carried out a December 2021 decision of the Wassenaar Arrangement, the multilateral export-control group^[17].

In late May 2025 the US Bureau of Industry and Security, the agency that writes export licenses, told the design-software vendors that sales to China now needed a license^[1]. Cadence got its letter on 23 May: exporting design software classified 3D991 and 3E991 to any party in China, or to a Chinese military end user anywhere, now needed a license^[1]. Synopsys got its letter on 29 May and a rescinding letter on 2 July^[19].

Washington imposed the 2025 requirement alone, and at once. Synopsys's China revenue fell from 16 percent of its total in fiscal 2024 to 12 percent in fiscal 2025^[3]. SemiAnalysis links the decline to tighter export restrictions and to local design-software companies winning share at mature nodes^[3]. SemiAnalysis also quoted Synopsys's management saying that the companies it cannot sell to look for alternatives, typically local design-software and licensed-block companies^[3].

In October 2025 CSIS found that only a few companies, Cadence, Synopsys and Siemens, make design software that supports the entire chip design flow of more than 40 steps^[20]. In a January 2021 report built on 2019 market data, CSET at Georgetown University found that one Chinese firm, Empyrean, could reportedly run a complete design flow only for certain analog and mixed-signal chips, which combine analog and digital circuits^[21]. Outside that niche, Chinese designers then relied on US tools for all chip designs^[21]. The report found that other Chinese tools covered only narrow parts of the design flow or supplemented US tools, and largely did not support processes at 14 nm and below^[21]. In its 2025 annual report, filed in April 2026, Empyrean says it now has complete design flows for analog, memory, radio-frequency and flat-panel display circuits, and that its digital tools cover 80 percent of the main tools for digital design^[22]. The same report lists foundry certifications for its circuit simulator at 8, 5 and 4 nm and for its physical verification tool, the final layout check, at 28 nm^[22]. CSIS found that as of 2025 Chinese design tools were still far from replacing the full range of advanced capabilities US firms offer, especially for 5 nm and 3 nm chip design^[20].

China can design an accelerator. It cannot finish one at the leading edge without foreign tools, or build what it designs without foreign equipment. In June 2024 CSET found that SMIC's limited 7 nm capacity forced Huawei to choose between making its most advanced phone chips and its AI chips^[23].

On Epoch AI's estimates, Huawei's flagship chip for 2026, the Ascend 950, delivers about half the computing performance of Nvidia's H100, which began shipping in 2022, and Nvidia's B300 has 6.75 times the 950's theoretical peak performance^[24]. Epoch's median estimate is that Huawei will make about 1.5 million Ascend chips in 2026, against 5.9 million for Nvidia^[24]. On those estimates, Huawei's 2026 output would carry less than 4 percent of the computing power Nvidia ships that year^[24]. Epoch puts Huawei's chips three to four years behind Nvidia's until at least 2030, for three reasons. SMIC, which makes Huawei's chips, cannot pack transistors as densely as TSMC, which makes Nvidia's. Chinese memory makers are only starting to produce high-bandwidth memory. And Huawei's software for programming its chips is far less mature than Nvidia's^[24].

Key evaluation criteria

• Flow completeness. How many steps one vendor covers, from the first line of code to final signoff.
• Foundry certification. Whether the foundry has validated that exact tool version against its reference flow and process design kit, the file set describing what the factory can print. Without that, the foundry refuses signoff.
• Verification throughput. Simulation cycles and emulator capacity per day, which set the schedule more than anything else.
• IP availability at node. Whether the licensed blocks, the processor cores, the high-speed serial links, PCIe and the memory interface, have been proven in silicon on that process.
• Design services depth. Whether a partner can carry a customer's circuit list to a finished mask set on the newest node.
• Legal exposure. How much of the flow is US-origin technology, and so subject to export licensing.