Photomasks and Pellicles

Every EUV layer on an AI accelerator needs a flawless mask, built on a blank plate from one of only three suppliers worldwide, two of which are Japan's AGC and Hoya^[1]. AGC says it is the only company in the world that takes an EUV blank all the way from the glass to the finished coating^[2].

How it works

How a photomask prints its pattern

1. The scanner. A photomask is the stencil that lithography prints from, one for each layer of a chip. Inside the scanner, light bounces off the mask and carries its pattern down to the wafer.
2. A mirror. No glass lets the short light now in use pass through. So the mask is a mirror, built up from about forty pairs of very thin layers laid on glass, and the light bounces off it.
3. The pattern. A dark pattern drawn on the mirror soaks up the light wherever no line should print. The light that bounces back carries the pattern of one layer.
4. Wafer after wafer. The same mask prints its layer on wafer after wafer, so one plate shapes millions of chips.
5. One speck. A speck of dust on the mask prints on every wafer, until someone finds it. The pellicle, a dust cover meant to protect the mask, is still short of production in a leading-edge fab.

Simplified. The mask is drawn face down, as it sits in the scanner. The mirror layers and the dark pattern are drawn far thicker than they are, and the light's path through the scanner's mirrors is cut to one bounce.

ASML says a chip's most complicated layers are made on EUV machines, while the rest can often be printed on older deep ultraviolet machines^[3]. A mask starts as a blank, a polished plate with nothing on it yet. For deep ultraviolet the blank is a window of quartz carrying a light-blocking film such as molybdenum silicide, and Shin-Etsu supplies those blanks^[4]. For EUV the blank is a mirror of about 40 molybdenum and silicon layer pairs, 7 nm to a pair, laid on glass, with a dark tantalum film on top, the absorber, that will carry the pattern^[5].

The mask shop coats the blank with resist, and a mask writer draws the design into the coating with electrons. A single-beam writer flashes one shape at a time, while NuFlare's multi-beam writer for the most advanced masks controls 260,000 beams at once^[6]. A wash removes the drawn resist, an etch removes the blocking film or absorber wherever the resist is gone, and the rest of the resist is stripped. The plate now passes light, or reflects it, in the exact shape of one layer of the chip. On standard scanners it is drawn four times larger than it will print. An inspection tool compares the plate to the design, and a repair tool fixes the stray defects it finds.

Making the plate a mirror creates its own problems:

• Mask 3D effects. Light strikes the mirror at a slant, and the absorber has height, so its edges throw small shadows that distort the printed shape; software has to correct for it in advance.
• Write precision. Every edge of the absorber has to sit within a few nanometers of where the design says.
• Particles. Anything on the reflector prints on every wafer until someone finds it.

High-NA scanners, the newest EUV machines, print finer lines with larger mirrors. To keep masks at their usual size, their mirrors shrink the pattern four times in one direction and eight times in the other, so each exposure covers half the patch of wafer and a wafer takes twice as many exposures^[7]. On 8 September 2026 ASML and TSMC announced an initiative to move from today's 6-inch masks to 12-inch masks, which they expect to raise fab productivity, lower chipmaking costs and remove stitching constraints^[8]. They aim to set up a 12-inch mask pilot line by 2031, so that High-NA scanners using 12-inch masks can enter advanced chip production by 2033^[8].

Variants and trade-offs

Blanks

AGC says it invested more than a decade in meeting the blank's requirements, which include near-zero thermal expansion, perfectly smooth and flat surfaces and no particle contamination, and mass production only began in 2017^[1]. AGC publishes no share figure for EUV blanks, but it counts the suppliers. It says it is one of three companies worldwide that supply EUV blanks, and the only one that handles every material and process itself^[1]. Its own data book ranks AGC No.2 worldwide in EUV lithography photomask blanks, based on AGC's fiscal 2026 estimates^[9].

Hoya says its share of the mask blank market is exceptionally high, and that customers may gradually move toward multi-sourcing EUV blanks^[10]. In April 2023 AGC said its EUV blank capacity would grow by about 30 percent in 2025, on a line in Fukushima selected under a METI supply-chain program, and that it was aiming for more than ¥40 billion of sales in the business by 2025^[2]. In December 2024 AGC said its EUV blank sales had grown 50 percent in 2023^[1]. The sales reached ¥40 billion in 2024, a year ahead of the 2025 target, AGC reported in February 2025^[11]. In June 2026 AGC said they had declined in 2025 and were on a recovery track in 2026^[12]. In August 2026 AGC planned capacity expansions of 20 to 50 percent across EUV blanks, polishing slurry and lens materials for lithography tools, with no separate figure for the blanks, and mass production on the added capacity to begin in 2028^[13].

Writers

An electron-beam writer cuts the pattern into a sensitive coating on the blank. Multi-beam writers fire many beams at once, and Japan's NuFlare sells them for 3 nm node design rules^[6]. In September 2023 Intel called Austria's IMS Nanofabrication the established industry leader in the multi-beam mask writing tools that advanced EUV requires, and agreed to sell roughly 10 percent of it to TSMC at a valuation of about $4.3 billion^[14]. TSMC's subsidiary TSMC Development held that 10 percent at the end of 2024, at a fair value of $432.8 million in TSMC's accounts^[15]. Intel sold a combined 32 percent of IMS in 2023 and still held the other 68 percent on 27 December 2025^[16]. Counting all electron-beam mask writers, CSET put IMS's share of a $994 million world market at 46.6 percent in 2025, ahead of NuFlare at 39.2 percent and JEOL at 14.2 percent^[17].

Inspection and repair

A mask defect costs yield on every wafer that mask prints, so fabs check masks three times: as blanks, after patterning and again in production. Actinic inspection uses 13.5 nm light, the wavelength of EUV lithography, and Lasertec launched the world's first actinic EUV patterned mask inspection system, the ACTIS A150, in 2019^[18]. In October 2025 it launched the ACTIS A200HiT series, which it says triples the A150's inspection speed^[18]. Lasertec reported net sales of JPY 230,485 million in the year to June 2026^[19]. KLA sells optical reticle inspection tools for both EUV and optical masks^[20]. Zeiss makes AIMS EUV, which checks a mask in EUV light under the scanner's own imaging conditions to judge how a defect will affect printing, and says it can be extended to ASML's High-NA scanner, the EXE:5000^[21]. Zeiss also sells electron-beam repair tools that work on EUV masks^[22].

Pellicles

A pellicle is a thin membrane on a frame above the mask. Particles land on it, too far out of focus to print, and the pattern below stays clean.

ASML's EUV membrane is 13 nanometers thick, has to hold together at 500 degrees Celsius in vacuum, and every photon it absorbs is light that never reaches the wafer^[23]. ASML released its first EUV pellicles in 2016 and calls the pellicle one of the breakthroughs that brought EUV lithography to high-volume manufacturing^[23]. The light crosses it twice, on the way in and on the way back off the mirror, so absorption counts double.

Carbon nanotube membranes are the next step, aimed at next-generation High-NA, high-output EUV scanners^[24]. In 2020 imec mounted them on reticles and exposed them in an NXE:3300 scanner, measuring single-pass transmission up to 97 percent and finding the effect on imaging low and correctable^[25]. Mitsui Chemicals, which began commercial production of silicon-based EUV pellicles under an ASML license in 2021, said in 2024 it would build a plant at Iwakuni-Ohtake, tentatively due to finish in December 2025, for carbon nanotube membranes with 92 percent or higher transmittance that withstand exposure power above 1 kW^[24].

Cost and design economics

In July 2022 SemiAnalysis put mask sets beyond $1 million at 28 nm and beyond $10 million at 7 nm, and expected 3 nm mask sets to push into the $40 million range^[26]. Its May 2026 primer still puts a leading-edge mask set at $40 million, and a single respin, remaking a chip after a design flaw, at leading-edge nodes at $50 million to $100 million^[27].

That cost decides who can use a node at all. SemiAnalysis wrote that falling cost per transistor at 5 nm and 3 nm is limited to firms with large wafer volume, and that more companies will lack the volume to spread the fixed cost of mask sets^[26]. It expected failed chip designs to show up first among AI chip startups, which work on much tighter budgets^[26].

What one mask set costs, by node, 2022 ($M). The 28 nm and 7 nm figures are minimums and 3 nm was a projection$M

What one mask set costs, by node, 2022 ($M). The 28 nm and 7 nm figures are minimums and 3 nm was a projection

28 nm	1 $M
7 nm	10 $M
3 nm	40 $M

Source: SemiAnalysis, The Dark Side of the Semiconductor Design Renaissance, July 2022. SemiAnalysis's May 2026 EDA Market Primer puts a leading-edge mask set at $40M

Who makes it

Mask making splits between chipmakers that make masks for their own use and independent merchant firms that sell to them and others^[28]. Photronics says the market was majority captive-supplied for a period, and that production has more recently tended to move toward the independents^[28]. Photronics, a leading worldwide maker of IC and flat panel display masks, had $849.3 million of fiscal 2025 revenue, of which $615.1 million was IC masks^[29]. Its named competitors in chip and display masks include Dai Nippon Printing, Hoya, Tekscend Photomask and two Chinese firms, Shenzhen Newway Photomask and Shenzhen Qingyi Photomask, and it also competes with chipmakers' own mask shops^[28].

SMIC runs two in-house mask shops in Shanghai, for g-line, i-line, DUV and ArF steppers and scanners^[30]. Photronics began operating two mask plants in China, in Hefei and Xiamen, in 2019, and its chip mask business in Xiamen is a joint venture in which DNP holds 49.99 percent^[28]. There is no Chinese EUV blank, no Chinese actinic inspection tool and no Chinese multi-beam writer.

The chokepoint

Mask blanks are a small, highly concentrated business. Three firms supply EUV blanks worldwide, AGC says, and AGC spent more than a decade meeting the blank's requirements before mass production began in 2017^[1]. AGC said in June 2026 that its EUV blank sales reached ¥40 billion in 2024, declined in 2025 and were recovering in 2026^[12]. Lasertec launched the first tool that inspects patterned EUV masks in EUV light, in 2019^[18].

Pellicles already work in high-volume EUV manufacturing, but ASML says no material is completely transparent to EUV light, so any pellicle in the light's path costs customers productivity^[23]. In 2024 Mitsui Chemicals said it would set up production of carbon nanotube membranes for next-generation High-NA, high-output EUV scanners^[24].

Key evaluation criteria

• Blank defectivity. Particles buried in the multilayer cannot be repaired, so blank yield sets mask yield.
• Write time and placement. Intel said in 2023 that advanced EUV requires multi-beam mask writing tools, and called IMS the established industry leader in them^[14]. In 2025 IMS held 46.6 percent of the market for all electron-beam mask writers, on CSET's count^[17].
• Actinic inspectability. A 13.5 nm inspection uses the same wavelength as EUV lithography, and Lasertec launched the first one for patterned masks in 2019^[18].
• Pellicle transmission and lifetime. Transmission counts twice, and imec measured carbon nanotube membranes passing up to 97 percent in a single crossing in 2020^[25].
• Mask-set cost per node. In July 2022 SemiAnalysis put a set above $10M at 7 nm, a cost that decides which designs can use a node^[26]. In May 2026 it put a leading-edge set at $40M^[27].