Test and Assembly

Turning silicon into a finished, packaged chip takes 1,000 to 1,500 steps, depending on how complex the chip is, the Semiconductor Industry Association estimated in 2025^[1]. Advantest's investor guide of July 2026 counts test as the only step that puts electrical signals through the chip^[2]. Every stage so far makes dies; the back end of the industry, assembly and test, decides which of them are allowed into a package.

How it works

How a chip is tested

1. The wafer. Every stage so far makes chips. Before any of them can be sold, a machine tests each one, starting while the chips are still on the wafer.
2. Needles. A probe card lowers thousands of needles onto one chip. They press onto small metal pads on its surface.
3. Questions and answers. Through the needles, the tester sends signals into the chip and reads what comes back. It checks every answer.
4. Chip by chip. The tester steps from chip to chip across the wafer. It marks any chip that answers wrong, and that chip goes no further.
5. Into the package. Only chips that pass go on to be packaged. A modern accelerator glues together a dozen expensive pieces, and one bad piece throws away all of them, so each piece is tested before it goes in.

Simplified. Nine needles stand for thousands, and the failed chips are placed for illustration and show no real yield. The package follows chapter 11: two logic chips and eight memory stacks on a silicon base and a package base.

Each round of test catches failures the round before it cannot see.

• Wafer sort. Thousands of needles land on each die while it is still on the wafer, a tester drives patterns in and checks the answers, and the failures go no further.
• Burn-in. Run the part hot and at raised voltage for minutes to days, on the wafer or in the package, so anything that would fail early fails in the factory^[3].
• Final test. The tester runs the packaged part again, because packaging adds failures of its own.
• System-level test. The finished part sits in a socket and runs something close to a real workload, because some failures appear only when everything runs at once.

Proving a die good before it is packaged matters more as packages hold more valuable parts^[4]. Aehr's wafer-level burn-in systems look for early-life and hidden failures before dies are cut from the wafer, which lowers the risk of committing high-bandwidth memory and an expensive substrate to a processor that may later fail^[4]. Aehr's lead AI customer is shifting burn-in for its AI accelerators from the finished system to the wafer^[5]. The FOX-XP systems that customer ordered from Aehr in August 2026 each burn in nine 300 mm wafers at a time^[4].

Variants and trade-offs

Wafer sort and known-good die

The probe card that holds those needles is the hard part. FormFactor says the high-frequency capability of its probe cards lets it compete favorably in testing high-bandwidth memory, a stack of eight, twelve or even sixteen memory dies^[6]. For a large logic die every needle must sit in the same plane, survive repeated touchdowns without drifting, and do it hot. Cards are custom to the device, so each new part means a new card and a new qualification.

Final test, burn-in and system-level test

The economics get worse as packages grow. TSMC has told investors that its CoWoS packaging roadmap runs beyond 14 times the area a lithography machine can print in one shot^[7]. Every added die is another chance to lose the whole assembly, along with its memory and substrate^[4]. ASE ran 6,797 testers in the second quarter of 2025 and 8,348 a year later^[8].

Automated test equipment: share of the ~$9.0bn tester market, 2025%

Advantest65%Teradyne and all others35%

Source: Advantest FY2025 results briefing, April 2026

Who makes it

Advantest puts its own share at about 65 percent of an estimated $9.0 billion tester market in 2025^[9]. Its share of system-on-chip (SoC) testers, the machines that test processors and other non-memory chips, rose about ten points in a year to 66 percent, and it held about 60 percent of memory test^[9]. Teradyne, its main rival, took $2.52 billion of semiconductor test revenue in 2025, service included, of which $1.89 billion came from SoC testers and $505 million from memory testers^[10]. Teradyne as a whole grew 13 percent to $3.19 billion for 2025, with fourth-quarter revenue up 44 percent on AI demand^[11].

Where the tester money went in calendar 2025$bn

SoC testers6.9Memory testers2.1

Source: Advantest FY2025 results briefing, April 2026

Below the two tester makers, the rest of the test and assembly equipment splits into niches, each with its own suppliers.

• Probe cards. FormFactor took $785.0 million in fiscal 2025^[12]; Technoprobe grew 15.7 percent to EUR 628.4 million, about 38 percent of it from AI, and aims to double capacity by the end of 2027^[13].
• Probers, the machines that move each wafer under the probe card and keep it at a set temperature. Tokyo Seimitsu, which sells as Accretech, says it has the top global share in probers and also makes dicing machines and grinders^[14]. Tokyo Electron also makes probers^[15].
• Handlers and burn-in, the machines that feed parts into a tester and heat them. Cohu took $453.0 million in fiscal 2025^[16]; Aehr did $50.0 million in fiscal 2026 but booked a record $60.7 million in the fourth quarter alone and guides to $130 million to $150 million in fiscal 2027^[5].
• Dicing and grinding. In 2025 Disco held 87 percent and Accretech 8.1 percent of a $1.9 billion market for the saws that cut wafers into dies and the grinders that thin them, according to CSET's analysis of TechInsights data^[17]. In December 2025 Disco announced a saw that cuts packages up to 400 by 400 mm^[18].
• Bonding. Kulicke and Soffa did $654.1 million in fiscal 2025^[19], while Besi's second-quarter 2026 revenue rose 68.7 percent to EUR 249.9 million on hybrid bonding and data center demand^[20].

Thermocompression bonders press memory dies into a stack and place chiplets on substrates. ASMPT says it remained the leader in that market in 2025 and aims for a 35 to 40 percent share^[21]. In its 2025 results it said it expects the market to reach $1.6 billion by 2028^[21]. It took a repeat order for fifteen chip-to-substrate bonders in December 2025^[22]. Hanmi Semiconductor in Korea also sells thermocompression bonders, including dual bonders for high-bandwidth memory^[23]. See Memory and HBM.

The back end's geography

Outsourced assembly and test, the OSAT business, is Taiwanese with a large Chinese challenger. ASE, the biggest, billed $20.6 billion in 2025^[24]. About 59 percent of that came from packaging and test and 40 percent from its electronics manufacturing arm^[25]. Georgetown's CSET counts four of the top ten OSATs by 2024 revenue as China-headquartered^[26]. Malaysia's investment agency said in July 2026 that the country ships 13 percent of the world's packaged chips and wants 7 percent of advanced packaging shipments by 2035^[27]. A 2024 study by the Semiconductor Industry Association and Boston Consulting Group measured factory floor space at contractors and chipmakers' own plants, and gave Malaysia 7 percent of global assembly, test and packaging capacity in 2022, the largest share in Southeast Asia^[28].

ASE spent $2.7 billion on machinery and $1.4 billion on buildings, facilities and automation in the first half of 2026, and says revenue from leading-edge advanced packaging is running ahead of its $3.5 billion guidance for the year^[29]. Powertech aims to run the first panel-level packaging line for AI chips in 2027^[30].

Amkor took $6.71 billion of revenue in 2025^[31], and $1.90 billion in the second quarter of 2026 alone, up 26 percent year on year^[32]. It has expanded its Arizona campus to a $7 billion investment^[33]. In October 2024 TSMC and Amkor signed a memorandum of understanding under which TSMC would buy packaging and test services from Amkor's planned plant in Peoria, Arizona, to serve TSMC customers, especially those using its Phoenix fabs^[34]. The two announced a long-term partnership in June 2026^[35].

Testers installed at ASE, the largest assembly and test contractortesters

Testers installed at ASE, the largest assembly and test contractor

Q2 2025	6,797 testers
Q1 2026	7,585 testers
Q2 2026	8,348 testers

Source: ASE Technology Holding, second quarter 2026 earnings release (SEC Form 6-K)

The chokepoint

Unlike lithography, no test or assembly tool has a single supplier. Advantest argues that switching tester vendor means rebuilding the whole development, evaluation and production test environment, which is why share moves slowly^[36].

Between 2019 and 2024, CSET finds, Chinese toolmakers gained 5 percentage points of share in test tools and 4 points in fabrication tools built for advanced packaging, but lost share in bonding and other conventional assembly and packaging tools^[26]. They still lag significantly behind foreign suppliers^[26]. ASE's packaging and test business took about $12.1 billion from outside customers in 2025^[37]. With Amkor's $6.71 billion, the two billed about $18.8 billion between them, against industry sales of $791.7 billion^[38]. That is a small share of the money for a step every chip has to pass through.

Key evaluation criteria

• Test coverage is the share of hidden failures caught before they reach a package that cannot be taken apart.
• Test time per part sets throughput and cost, and large dies, memory stacks and chiplets all push it up.
• Probe card flatness and life decide what wafer sort costs. Every needle must stay in the same plane across a full die and hold that over a long life.
• Thermal control matters more every generation. A kilowatt-class accelerator has to be held at temperature in the socket while it is tested at speed.
• Capacity and geography are the practical constraint. Taiwan, China and Malaysia hold most of the floor space, and new capacity takes years.